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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 tms320f2806x piccolo ? microcontrollers 1 device overview 1 1.1 features 1 ? high-efficiency 32-bit cpu (tms320c28x) ? 90 mhz (11.11-ns cycle time) ? 16 16 and 32 32 multiply and accumulate (mac) operations ? 16 16 dual mac ? harvard bus architecture ? atomic operations ? fast interrupt response and processing ? unified memory programming model ? code-efficient (in c/c++ and assembly) ? floating-point unit (fpu) ? native single-precision floating-point operations ? programmable control law accelerator (cla) ? 32-bit floating-point math accelerator ? executes code independently of the main cpu ? viterbi, complex math, crc unit (vcu) ? extends c28x instruction set to support complex multiply, viterbi operations, and cyclic redundency check (crc) ? embedded memory ? up to 256kb of flash ? up to 100kb of ram ? 2kb of one-time programmable (otp) rom ? 6-channel direct memory access (dma) ? low device and system cost ? single 3.3-v supply ? no power sequencing requirement ? integrated power-on reset and brown-out reset ? low-power operating modes ? no analog support pin ? endianness: little endian ? jtag boundary scan support ? ieee standard 1149.1-1990 standard test access port and boundary scan architecture ? clocking ? two internal zero-pin oscillators ? on-chip crystal oscillator/external clock input ? watchdog timer module ? missing clock detection circuitry ? peripheral interrupt expansion (pie) block that supports all peripheral interrupts ? three 32-bit cpu timers ? advanced control peripherals ? up to 8 enhanced pulse-width modulator (epwm) modules ? 16 pwm channels total (8 hrpwm-capable) ? independent 16-bit timer in each module ? three input enhanced capture (ecap) modules ? up to 4 high-resolution capture (hrcap) modules ? up to 2 enhanced quadrature encoder pulse (eqep) modules ? 12-bit analog-to-digital converter (adc), dual sample-and-hold (s/h) ? up to 3.46 msps ? up to 16 channels ? on-chip temperature sensor ? 128-bit security key and lock ? protects secure memory blocks ? prevents reverse-engineering of firmware ? serial port peripherals ? two serial communications interface (sci) [uart] modules ? two serial peripheral interface (spi) modules ? one inter-integrated-circuit (i 2 c) bus ? one multichannel buffered serial port (mcbsp) bus ? one enhanced controller area network (ecan) ? universal serial bus (usb) 2.0 (see device comparison table for availability) ? full-speed device mode ? full-speed or low-speed host mode ? up to 54 individually programmable, multiplexed general-purpose input/output (gpio) pins with input filtering ? advanced emulation features ? analysis and breakpoint functions ? real-time debug through hardware ? 2806x packages ? 80-pin pfp and 100-pin pzp powerpad ? thermally enhanced thin quad flatpacks (htqfps) ? 80-pin pn and 100-pin pz low-profile quad flatpacks (lqfps) sample &buy productfolder support &community tools & software technical documents
2 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 device overview copyright ? 2010 ? 2016, texas instruments incorporated 1.2 applications ? switch mode power supplies (smpss) ? solar micro inverters and converters ? power factor correction (pfc) ? smart grid and power line communications ? ac/dc inverters 1.3 description the f2806x piccolo ? family of microcontrollers (mcus) provides the power of the c28x core and cla coupled with highly integrated control peripherals in low pin-count devices. this family is code-compatible with previous c28x-based code, and also provides a high level of analog integration. an internal voltage regulator allows for single-rail operation. enhancements have been made to the high- resolution pulse width modulator (hrpwm) module to allow for dual-edge control (frequency modulation). analog comparators with internal 10-bit references have been added and can be routed directly to control the epwm outputs. the adc converts from 0 to 3.3-v fixed full-scale range and supports ratio-metric v refhi /v reflo references. the adc interface has been optimized for low overhead and latency. (1) for more information on these devices, see section 9 , mechanical packaging and orderable information. device information (1) part number package body size tms320f28069pzp htqfp (100) 14.0 mm 14.0 mm tms320f28069pfp htqfp (80) 12.0 mm 12.0 mm tms320f28069pz lqfp (100) 14.0 mm 14.0 mm tms320f28069pn lqfp (80) 12.0 mm 12.0 mm
3 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 device overview copyright ? 2010 ? 2016, texas instruments incorporated 1.4 functional block diagram figure 1-1 shows a functional block diagram of the device. a. not all peripheral pins are available at the same time due to multiplexing. figure 1-1. functional block diagram cla bus dma bus dma bus 16-bit peripheral bus 32-bit peripheral bus memory bus a7:0b7:0 memory bus memory bus dma bus cla bus dma bus gpio mux aio mux 32-bit peripheral bus adc 0-wait result regs adc comp + dac comp1out comp2out comp3out comp1a comp2a comp3a comp1b comp2b comp3b boot-rom (32k 16) (0-wait, non-secure) gpio mux gpio mux trst tck, tdi, tms tdo xclkin lpm wakeup 3 ext. interrupts x1 x2 xrs m0 saram (1k 16) (0-wait, non-secure) m1 saram (1k 16) (0-wait, non-secure) l5 dpsaram (8k 16) (0-wait, non-secure) dma ram0 l6 dpsaram (8k 16) (0-wait, non-secure) dma ram1 l7 dpsaram (8k 16) (0-wait, non-secure) dma ram2 l8 dpsaram (8k 16) (0-wait, non-secure) dma ram3 l0 dpsaram (2k 16) (0-wait, secure) cla data ram2 l1 dpsaram (1k 16) (0-wait, secure) cla data ram0 l2 dpsaram (1k 16) (0-wait, secure) cla data ram1 l3 dpsaram (4k 16) (0-wait, secure) cla program ram l4 saram (8k 16) (0-wait, secure) code security module (csm) pswd otp 1k 16 secure flash 128k 16 8 equal sectors secure 64k 16 pump otp/flash wrapper 32-bit peripheral bus usb-0 gpio mux scitxdx scirxdx spisimox spisomix spiclkx spistex sdax sclx mfsra mdra mclkra mfsxa mdxa mclkxa ecapx eqepxa eqepxb eqepxi eqepxs hrcapx canrxx cantxx usb0dp usb0dm tzx epwmxa epwmxb epwmsynci epwmsynco sci-asci-b (4l fifo) spi-aspi-b (4l fifo) i2c-a (4l fifo) 32-bit peripheral bus (cla accessible) epwm1 to epwm8 hrpwm (8ch) mcbsp-a 32-bit peripheral bus (cla accessible) ecap1ecap2 ecap3 eqep1eqep2 32-bit peripheral bus hrcap1hrcap2 hrcap3 hrcap4 ecan-a (32-mbox) cla + message rams dma 6-ch c28x 32-bit cpu fpu vcu osc1, osc2, ext, plls, lpm, wd, cpu timer 0, cpu timer 1, cpu timer 2, pie
4 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 device overview copyright ? 2010 ? 2016, texas instruments incorporated 1.5 system device diagram figure 1-2. peripheral blocks 10-bit dac analog comparators cmp1-outcmp2-out cmp3-out trip zone temp sensor adc (dma- accessible) 12-bit 3.46-msps dual sample- and- hold soc-based v ref cla core 90-mhz floating-point (accelerator) (dma-accessible) 10-bit dac 10-bit dac a0 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 a1 6 eqep 2 hrcap 4 ecap 3 system vreg int-osc-1 por/bor int-osc-2 on-chip osc wd pll clksel timers 32-bit timer-0 timer-1 timer-2 gpio control comms x1 x2 v reflo v refhi c28x core (90-mhz) fpu vcu flash memory ram ram (dual-access) eqep 8 hrcap 4 ecap 3 4 8 2 2 6 pwm-1apwm-1b pwm-2a pwm-2b pwm-3a pwm-3b pwm-4a pwm-4b pwm-5a pwm-5b pwm-6a pwm-6b pwm-7a pwm-7b pwm-8a pwm-8b tz1 tz2 tz3 cmp1-outcmp2-out cmp3-out pwm1 (dma-accessible) pwm5 (dma-accessible) pwm8 (dma-accessible) pwm7 (dma-accessible) pwm6 (dma-accessible) pwm4 (dma-accessible) pwm3 (dma-accessible) pwm2 (dma-accessible) uart 2 spi 2 i c 2 can mcbsp (dma-accessible) 2 usb (dma-accessible)
5 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 table of contents copyright ? 2010 ? 2016, texas instruments incorporated table of contents 1 device overview ......................................... 1 1.1 features .............................................. 1 1.2 applications ........................................... 2 1.3 description ............................................ 2 1.4 functional block diagram ............................ 3 1.5 system device diagram .............................. 4 2 revision history ......................................... 6 3 device comparison ..................................... 7 4 terminal configuration and functions .............. 9 4.1 pin diagrams ......................................... 9 4.2 signal descriptions .................................. 11 5 specifications ........................................... 19 5.1 absolute maximum ratings ........................ 19 5.2 esd ratings for tms320f2806xu ................. 19 5.3 esd ratings for tms320f2806x, tms320f2806xm, and tms320f2806xf .......... 19 5.4 recommended operating conditions ............... 20 5.5 electrical characteristics ............................ 20 5.6 power consumption summary ...................... 21 5.7 thermal resistance characteristics ................ 25 5.8 thermal design considerations .................... 27 5.9 emulator connection without signal buffering for the mcu ............................................. 27 5.10 parameter information .............................. 28 5.11 test load circuit .................................... 28 5.12 power sequencing .................................. 29 5.13 clock specifications ................................. 32 5.14 flash timing ........................................ 35 6 detailed description ................................... 37 6.1 overview ............................................ 37 6.2 memory maps ....................................... 47 6.3 register maps ....................................... 58 6.4 device emulation registers ......................... 60 6.5 vreg, bor, por .................................. 62 6.6 system control ...................................... 64 6.7 low-power modes block ............................ 73 6.8 interrupts ............................................ 74 6.9 peripherals .......................................... 79 7 applications, implementation, and layout ...... 156 7.1 ti design or reference design .................... 156 7.2 development tools ................................ 157 7.3 software tools ..................................... 157 7.4 training ............................................ 158 8 device and documentation support .............. 159 8.1 device support ..................................... 159 8.2 documentation support ............................ 161 8.3 related links ...................................... 162 8.4 community resources ............................. 162 8.5 trademarks ........................................ 162 8.6 electrostatic discharge caution ................... 162 8.7 glossary ............................................ 162 9 mechanical packaging and orderable information ............................................. 163 9.1 packaging information ............................. 163
6 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 revision history copyright ? 2010 ? 2016, texas instruments incorporated 2 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from july 2, 2014 to march 22, 2016 (from e revision (july 2014) to f revision) page ? global: changed " can 2.0b " to " iso11898-1 (can 2.0b) " . .................................................................. 1 ? table 3-1 (device comparison): changed the number of high-resolution epwm channels on the 80-pin pn/pfp packages from 6 to 8. ..................................................................................................... 7 ? table 3-1 : removed " product status " row and associated footnote. ......................................................... 7 ? figure 4-1 (80-pin pn and pfp packages (top view)): added footnote about powerpad. .............................. 9 ? figure 4-2 (100-pin pz and pzp packages (top view)): added footnote about powerpad. ........................... 10 ? section 4.2 (signal descriptions): added " gpio26 ? 27 " to note. .......................................................... 11 ? table 4-1 (signal descriptions): updated description of x1, v refhi , v reflo , and v ddio . ............................. 11 ? section 5.1 (absolute maximum ratings): added input voltage, v in (x1). ................................................. 19 ? section 5.1 : added t stg . ........................................................................................................... 19 ? section 5.2 (esd ratings for tms320f2806xu): added section. ........................................................... 19 ? section 5.3 (esd ratings for tms320f2806x, tms320f2806xm, and tms320f2806xf): changed title from " handling ratings " to " esd ratings for tms320f2806x, tms320f2806xm, and tms320f2806xf " . ................. 19 ? section 5.3 : updated footnotes. .................................................................................................. 19 ? section 5.4 (recommended operating conditions): removed footnote that read " v ddio and v dda should be maintained within approximately 0.3 v of each other " . ........................................................................ 20 ? section 5.6 (power consumption summary): changed section title from " current consumption " to " power consumption summary " . .......................................................................................................... 21 ? section 5.12 (power sequencing): updated paragraph that reads " there is no power sequencing requirement needed ... " . .......................................................................................................................... 29 ? table 5-10 (xclkout switching characteristics (pll bypassed or enabled)): added max value for t f(xco) ........ 34 ? table 5-10 : added max value for t r(xco) ......................................................................................... 34 ? table 5-15 (flash/otp access timing): removed footnote. ................................................................. 36 ? figure 6-1 (28069 memory map): added " fast and spintac libraries " block. changed size of boot rom. ........ 48 ? figure 6-2 (28068 memory map): added " fast and spintac libraries " block. changed size of boot rom. ....... 49 ? figure 6-3 (28067 memory map): added figure. ............................................................................... 50 ? figure 6-8 (28062 memory map): added " fast and spintac libraries " block. changed size of boot rom. ........ 55 ? section 6.6.2 (crystal oscillator option): added paragraph that begins " the on-chip crystal oscillator x1 and x2 pins are 1.8-v level signals ... " . ................................................................................................... 67 ? section 6.9.6.1.2 (mcbsp as spi master or slave timing): replaced " for all spi slave modes ... " paragraphs with " for all spi slave modes ... " table footnotes. ............................................................................ 115 ? table 6-44 (mcbsp as spi master or slave timing requirements (clkstp = 10b, clkxp = 0)): added " for all spi slave modes ... " footnote. ................................................................................................... 115 ? table 6-46 (mcbsp as spi master or slave timing requirements (clkstp = 11b, clkxp = 0)): added " for all spi slave modes ... " footnote. ................................................................................................... 116 ? table 6-48 (mcbsp as spi master or slave timing requirements (clkstp = 10b, clkxp = 1)): added " for all spi slave modes ... " footnote. ................................................................................................... 117 ? table 6-50 (mcbsp as spi master or slave timing requirements (clkstp = 11b, clkxp = 1)): added " for all spi slave modes ... " footnote. ................................................................................................... 118 ? table 6-65 (hrcap registers): added reference to footnote for hciclr and hcifrc. .............................. 137 ? section 7 (applications, implementation, and layout): added section. .................................................... 156 ? section 8.1.1.1 (getting started): updated links. ............................................................................. 159 ? figure 8-1 (device nomenclature): updated list of devices. ................................................................ 160 ? section 8.2 (documentation support): added the calculating useful lifetimes of embedded processors application report (sprabx4) to list of application reports. ............................................................... 161 ? section 8.2.1 (receiving notification of document updates): added section. ............................................ 162
copyright ? 2010 ? 2016, texas instruments incorporated device comparison submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 7 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 3 device comparison (1) a type change represents a major functional feature difference in a peripheral module. within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. these device-specific differences are listed in the tms320x28xx, 28xxx dsp peripheral reference guide ( spru566 ) and in the peripheral reference guides. (2) usb is present on tms320f2806xu, tms320f2806xm, and tms320f2806xf devices. (3) the " q " temperature option is not available on the tms320f2806xu devices. (4) tms320f2806xm devices are instaspin-motion-enabled mcus. tms320f2806xf devices are instaspin-foc-enabled mcus. for more information, see section 8.2 for a list of instaspin technical reference manuals. table 3-1. device comparison feature type (1) 28069 28069u (2) (3) 28069m (2) (4) 28069f (2) (4) (90 mhz) 28068 28068u (2) (3) 28068m (2) (4) 28068f (2) (4) (90 mhz) 28067 28067u (2) (3) (90 mhz) 28066 28066u (2) (3) (90 mhz) 28065 28065u (2) (3) (90 mhz) 28064 28064u (2) (3) (90 mhz) 28063 28063u (2) (3) (90 mhz) 28062 28062u (2) (3) 28062f (2) (4) (90 mhz) package type (pfp and pzp are powerpad htqfps. pn and pz are lqfps.) 100-pin pz pzp 80-pin pn pfp 100-pin pz pzp 80-pin pn pfp 100-pin pz pzp 80-pin pn pfp 100-pin pz pzp 80-pin pn pfp 100-pin pz pzp 80-pin pn pfp 100-pin pz pzp 80-pin pn pfp 100-pin pz pzp 80-pin pn pfp 100-pin pz pzp 80-pin pn pfp instruction cycle ? 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns floating-point unit (fpu) yes yes yes yes yes yes yes yes vcu yes yes no no yes yes no no cla 0 yes no no no yes no no no 6-channel dma 0 yes yes yes yes yes yes yes yes on-chip flash (16-bit word) ? 128k 128k 128k 128k 64k 64k 64k 64k on-chip saram (16-bit word) ? 50k 50k 50k 34k 50k 50k 34k 26k code security for on-chip flash, saram, and otp blocks ? yes yes yes yes yes yes yes yes boot rom (32k 16) ? yes yes yes yes yes yes yes yes one-time programmable (otp) rom (16-bit word) ? 1k 1k 1k 1k 1k 1k 1k 1k epwm channels 1 16 14 16 14 16 14 16 14 16 14 16 14 16 14 16 14 high-resolution epwm channels 1 8 8 8 8 8 8 8 8 ecap inputs 0 3 3 3 3 3 3 3 3 hrcap 0 4 1 4 1 4 1 4 1 4 1 4 1 4 1 4 1 eqep modules 0 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 watchdog timer ? yes yes yes yes yes yes yes yes 12-bit adc msps 3 3.46 3.46 3.46 3.46 3.46 3.46 3.46 3.46 conversion time 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns channels 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 temperature sensor yes yes yes yes yes yes yes yes dual sample-and-hold yes yes yes yes yes yes yes yes 32-bit cpu timers ? 3 3 3 3 3 3 3 3 comparators with integrated dacs 0 3 3 3 3 3 3 3 3 i 2 c 0 1 1 1 1 1 1 1 1
copyright ? 2010 ? 2016, texas instruments incorporated device comparison submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 8 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com table 3-1. device comparison (continued) feature type (1) 28069 28069u (2) (3) 28069m (2) (4) 28069f (2) (4) (90 mhz) 28068 28068u (2) (3) 28068m (2) (4) 28068f (2) (4) (90 mhz) 28067 28067u (2) (3) (90 mhz) 28066 28066u (2) (3) (90 mhz) 28065 28065u (2) (3) (90 mhz) 28064 28064u (2) (3) (90 mhz) 28063 28063u (2) (3) (90 mhz) 28062 28062u (2) (3) 28062f (2) (4) (90 mhz) package type (pfp and pzp are powerpad htqfps. pn and pz are lqfps.) 100-pin pz pzp 80-pin pn pfp 100-pin pz pzp 80-pin pn pfp 100-pin pz pzp 80-pin pn pfp 100-pin pz pzp 80-pin pn pfp 100-pin pz pzp 80-pin pn pfp 100-pin pz pzp 80-pin pn pfp 100-pin pz pzp 80-pin pn pfp 100-pin pz pzp 80-pin pn pfp (5) " q " refers to q100 qualification for automotive applications. mcbsp 1 1 1 1 1 1 1 1 1 ecan 0 1 1 1 1 1 1 1 1 spi 1 2 2 2 2 2 2 2 2 sci 0 2 2 2 2 2 2 2 2 usb 0 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2-pin oscillator 1 1 1 1 1 1 1 1 0-pin oscillator 2 2 2 2 2 2 2 2 i/o pins (shared) gpio ? 54 40 54 40 54 40 54 40 54 40 54 40 54 40 54 40 aio ? 6 6 6 6 6 6 6 6 external interrupts ? 3 3 3 3 3 3 3 3 supply voltage (nominal) ? 3.3 v 3.3 v 3.3 v 3.3 v 3.3 v 3.3 v 3.3 v 3.3 v temperature options t: ? 40 c to 105 c ? pz pn pz pn pz pn pz pn pz pn pz pn pz pn pz pn s: ? 40 c to 125 c ? pzp pfp pzp pfp pzp pfp pzp pfp pzp pfp pzp pfp pzp pfp pzp pfp q: ? 40 c to 125 c (3) (5) ? pzp pfp pzp pfp pzp pfp pzp pfp pzp pfp pzp pfp pzp pfp pzp pfp
9 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 terminal configuration and functions copyright ? 2010 ? 2016, texas instruments incorporated 4 terminal configuration and functions 4.1 pin diagrams figure 4-1 shows the pin assignments on the 80-pin pn and pfp packages. figure 4-2 shows the pin assignments on the 100-pin pz and pzp packages. a. pin 19: v refhi and adcina0 share the same pin on the 80-pin pn and pfp devices and their use is mutually exclusive to one another. pin 21: v reflo is always connected to v ssa on the 80-pin pn and pfp devices. b. the powerpad is not connected to the ground on the die. to facilitate effective heat dissipation, the powerpad must be connected to the ground plane of the pcb. it should not be left unconnected. for more details, see the powerpad ? thermally enhanced package application report ( slma002 ). figure 4-1. 80-pin pn and pfp packages (top view) 60 5958 57 56 55 54 53 52 51 50 4948 47 40 3938 37 36 35 34 33 32 31 30 2928 27 6162 63 64 65 66 67 68 69 70 71 72 73 74 12 3 4 5 6 7 8 9 10 11 1213 14 46 45 44 43 42 41 1516 17 18 19 20 7576 77 78 79 80 26 25 24 23 22 21 gpio23/eqep1i/mfsxa/scirxdb v dd v dd v ss v ddio gpio20/eqep1a/mdxa/comp1out gpio21/eqep1b/mdra/comp2out gpio4/epwm3a gpio5/epwm3b/spisimoa/ecap1 xrs trst v ss v ddio adcina6/comp3a/aio6 adcina5 adcina4/comp2a/aio4 adcina2/comp1a/aio2 adcina1 adcina0, v refhi v dda gpio10/epwm6a/adcsocbo gpio11/epwm6b/scirxdb/ecap1 gpio36/tms gpio35/tdi gpio37/tdo gpio34/comp2out/comp3out gpio38/xclkin/tck gpio39 gpio19/xclkin/ /scirxdb/ecap1 spistea v dd v ss v ddio x1x2 gpio6/epwm4a/epwmsynci/epwmsynco gpio7/epwm4b/scirxda/ecap2 gpio16/spisimoa/tz2 gpio8/epwm5a/adcsocao gpio17/spisomia/tz3 gpio18/spiclka/scitxdb/xclkout gpio26/ecap3/spiclkb/usb0dp gpio27/hrcap2/spisteb/usb0dm v ddio v ss v dd gpio3/epwm2b/spisomia/comp2out gpio2/epwm2a gpio1/epwm1b/comp1out gpio0/epwm1a gpio15/ecap2/scirxdb/spisteb vregenz v dd v ss v ddio gpio13/ /spisomib tz2 gpio14/ /scitxdb/spiclkb tz3 gpio24/ecap1/spisimob gpio22/eqep1s/mclkxa/scitxdb gpio32/sdaa/epwmsynci/adcsocao gpio33/scla/epwmsynco/adcsocbo gpio29/scitxda/scla/tz3 gpio12/ /scitxda/spisimob tz1 test2 v dd3vfl v ss gpio9/epwm5b/scitxdb/ecap3 gpio28/scirxda/sdaa/tz2 gpio30/canrxa/epwm7agpio31/cantxa/epwm8a gpio25/ecap2/spisomib v dd v ss v ddio adcinb6/comp3b/aio14adcinb5 adcinb4/comp2b/aio12 adcinb2/comp1b/aio10 adcinb1 adcinb0 v , v reflo ssa
10 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 terminal configuration and functions copyright ? 2010 ? 2016, texas instruments incorporated a. the powerpad is not connected to the ground on the die. to facilitate effective heat dissipation, the powerpad must be connected to the ground plane of the pcb. it should not be left unconnected. for more details, see the powerpad ? thermally enhanced package application report ( slma002 ). figure 4-2. 100-pin pz and pzp packages (top view) 75 74 73 72 71 70 6968 67 66 65 64 63 62 50 4948 47 46 45 44 43 42 41 40 3938 37 7677 78 79 80 81 82 83 84 85 86 87 88 89 12 3 4 5 6 7 8 9 10 11 12 13 14 61 60 5958 57 56 1516 17 18 19 20 9091 92 93 94 95 36 35 34 33 32 31 2122 23 24 25 30 2928 27 26 55 54 53 52 51 9697 98 99 100 v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ddio v ddio v ddio v ddio v refhi v ddio v ddio v dd3vfl v ssa test2 adcinb7adcinb3 x1x2 vregenz v reflo adcinb6/comp3b/aio14adcinb5 adcinb4/comp2b/aio12 adcinb2/comp1b/aio10 adcinb1 adcinb0 gpio0/epwm1a gpio1/epwm1b/comp1out gpio2/epwm2a gpio56/spiclka/eqep2i/hrcap3 gpio57/ /eqep2s/hrcap4 spistea gpio58/mclkra/scitxdb/epwm7a gpio40/epwm7a/scitxdb gpio41/epwm7b/scirxdb gpio3/epwm2b/spisomia/comp2out gpio6/epwm4a/epwmsynci/epwmsynco gpio44/mfsra/scirxdb/epwm7b gpio7/epwm4b/scirxda/ecap2 gpio8/epwm5a/adcsocao gpio9/epwm5b/scitxdb/ecap3 gpio10/epwm6a/adcsocbo gpio11/epwm6b/scirxdb/ecap1 gpio12/ /scitxda/spisimob tz1 gpio13/ /spisomib tz2 gpio14/ /scitxdb/spiclkb tz3 gpio15/ecap2/scirxdb/spisteb gpio16/spisimoa/tz2 gpio17/spisomia/tz3 gpio42/epwm8a/ /comp1out tz1 gpio43/epwm8b/ /comp2out tz2 gpio18/spiclka/scitxdb/xclkout gpio19/xclkin/ /scirxdb/ecap1 spistea gpio22/eqep1s/mclkxa/scitxdb gpio24/ecap1/eqep2a/spisimob gpio25/ecap2/eqep2b/spisomib gpio26/ecap3/eqep2i/spiclkb/usb0dp gpio27/hrcap2/eqep2s/spisteb/usb0dm gpio28/scirxda/sdaa/tz2 gpio29/scitxda/scla/tz3 gpio30/canrxa/eqep2i/epwm7a gpio50/eqep1a/mdxa/tz1 gpio51/eqep1b/mdra/tz2 gpio52/eqep1s/mclkxa/tz3 gpio53/eqep1i/mfsxa gpio54/spisimoa/eqep2a/hrcap1 gpio55/spisomia/eqep2b/hrcap2 gpio31/cantxa/eqep2s/epwm8a gpio32/sdaa/epwmsynci/adcsocao gpio33/scla/epwmsynco/adcsocbo gpio34/comp2out/comp3out gpio35/tdi gpio36/tms gpio37/tdo gpio38/xclkin/tckgpio39 gpio23/eqep1i/mfsxa/scirxdb gpio20/eqep1a/mdxa/comp1out gpio21/eqep1b/mdra/comp2out gpio4/epwm3a gpio5/epwm3b/spisimoa/ecap1 adcina7 adcina3 xrs trst adcina6/comp3a/aio6 adcina5 adcina4/comp2a/aio4 adcina2/comp1a/aio2 adcina1 adcina0 v dda
11 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 terminal configuration and functions copyright ? 2010 ? 2016, texas instruments incorporated 4.2 signal descriptions table 4-1 describes the signals. with the exception of the jtag pins, the gpio function is the default at reset, unless otherwise mentioned. the peripheral signals that are listed under them are alternate functions. some peripheral functions may not be available in all devices. see table 3-1 for details. inputs are not 5-v tolerant. all gpio pins are i/o/z and have an internal pullup (pu), which can be selectively enabled or disabled on a per-pin basis. this feature only applies to the gpio pins. the pullups on the pwm pins are not enabled at reset. the pullups on other gpio pins are enabled upon reset. the aio pins do not have an internal pullup. note when the on-chip voltage regulator (vreg) is used, the gpio19, gpio26 ? 27, and gpio34 ? 38 pins could glitch during power up. if this is unacceptable in an application, 1.8 v could be supplied externally. there is no power-sequencing requirement when using an external 1.8-v supply. however, if the 3.3-v transistors in the level-shifting output buffers of the i/o pins are powered before the 1.9-v transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power up. to avoid this behavior, power the v dd pins before or simultaneously with the v ddio pins, ensuring that the v dd pins have reached 0.7 v before the v ddio pins reach 0.7 v. table 4-1. signal descriptions (1) pin name pin no. i/o/z description pz pzp pn pfp jtag trst 12 10 i jtag test reset with internal pulldown (pd). trst, when driven high, gives the scan system control of the operations of the device. if this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. note: trst is an active-high test pin and must be maintained low at all times during normal device operation. an external pulldown resistor is required on this pin. the value of this resistor should be based on drive strength of the debugger pods applicable to the design. a 2.2-k ? resistor generally offers adequate protection. because this is application-specific, ti recommends validating each target board for proper operation of the debugger and the application. ( ) tck see gpio38 i see gpio38. jtag test clock with internal pullup. ( ) tms see gpio36 i see gpio36. jtag test-mode select (tms) with internal pullup. this serial control input is clocked into the tap controller on the rising edge of tck. ( ) tdi see gpio35 i see gpio35. jtag test data input (tdi) with internal pullup. tdi is clocked into the selected register (instruction or data) on a rising edge of tck. ( ) tdo see gpio37 o/z see gpio37. jtag scan out, test data output (tdo). the contents of the selected register (instruction or data) are shifted out of tdo on the falling edge of tck. (8-ma drive) flash v dd3vfl 46 37 3.3-v flash core power pin. this pin should be connected to 3.3 v at all times. test2 45 36 i/o test pin. reserved for ti. must be left unconnected.
12 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 terminal configuration and functions copyright ? 2010 ? 2016, texas instruments incorporated table 4-1. signal descriptions (1) (continued) pin name pin no. i/o/z description pz pzp pn pfp clock xclkout see gpio18 o/z see gpio18. output clock derived from sysclkout. xclkout is either the same frequency, one-half the frequency, or one-fourth the frequency of sysclkout. this is controlled by bits 1:0 (xclkoutdiv) in the xclk register. at reset, xclkout = sysclkout/4. the xclkout signal can be turned off by setting xclkoutdiv to 3. the mux control for gpio18 must also be set to xclkout for this signal to propogate to the pin. xclkin see gpio19 and gpio38 i see gpio19 and gpio38. external oscillator input. pin source for the clock is controlled by the xclkinsel bit in the xclk register, gpio38 is the default selection. this pin feeds a clock from an external 3.3-v oscillator. in this case, the x1 pin, if available, must be tied to gnd and the on-chip crystal oscillator must be disabled through bit 14 in the clkctl register. if a crystal or resonator is used, the xclkin path must be disabled by bit 13 in the clkctl register. note: designs that use the gpio38/xclkin/tck pin to supply an external clock for normal device operation may need to incorporate some hooks to disable this path during debug using the jtag connector. this is to prevent contention with the tck signal, which is active during jtag debug sessions. the zero-pin internal oscillators may be used during this time to clock the device. x1 60 48 i on-chip 1.8-v crystal-oscillator input. to use this oscillator, a quartz crystal or a ceramic resonator must be connected across x1 and x2. in this case, the xclkin path must be disabled by bit 13 in the clkctl register. if this pin is not used, it must be tied to gnd. x2 59 47 o on-chip crystal-oscillator output. a quartz crystal or a ceramic resonator must be connected across x1 and x2. if x2 is not used, it must be left unconnected. reset xrs 11 9 i/od device reset (in) and watchdog reset (out). piccolo devices have a built-in power-on reset (por) and brown-out reset (bor) circuitry. during a power-on or brown-out condition, this pin is driven low by the device. an external circuit may also drive this pin to assert a device reset. this pin is also driven low by the mcu when a watchdog reset occurs. during watchdog reset, the xrs pin is driven low for the watchdog reset duration of 512 oscclk cycles. a resistor between 2.2 k and 10 k should be placed between xrs and v ddio . if a capacitor is placed between xrs and v ss for noise filtering, it should be 100 nf or smaller. these values will allow the watchdog to properly drive the xrs pin to v ol within 512 oscclk cycles when the watchdog reset is asserted. regardless of the source, a device reset causes the device to terminate execution. the program counter points to the address contained at the location 0x3f ffc0. when reset is deactivated, execution begins at the location designated by the program counter. the output buffer of this pin is an open-drain with an internal pullup. ( ) adc, comparator, analog i/o adcina7 16 ? i adc group a, channel 7 input adcina6 17 14 i adc group a, channel 6 input comp3a i comparator input 3a aio6 i/o digital aio 6 adcina5 18 15 i adc group a, channel 5 input adcina4 19 16 i adc group a, channel 4 input comp2a i comparator input 2a aio4 i/o digital aio 4 adcina3 20 ? i adc group a, channel 3 input adcina2 21 17 i adc group a, channel 2 input comp1a i comparator input 1a aio2 i/o digital aio 2 adcina1 22 18 i adc group a, channel 1 input adcina0 23 19 i adc group a, channel 0 input. note: v refhi and adcina0 share the same pin on the 80-pin pn and pfp devices and their use is mutually exclusive to one another.
13 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 terminal configuration and functions copyright ? 2010 ? 2016, texas instruments incorporated table 4-1. signal descriptions (1) (continued) pin name pin no. i/o/z description pz pzp pn pfp v refhi 24 19 adc external reference high ? only used when in adc external reference mode. see section 6.9.2.1 . note: v refhi and adcina0 share the same pin on the 80-pin pn and pfp devices and their use is mutually exclusive to one another. adcinb7 35 ? i adc group b, channel 7 input adcinb6 34 27 i adc group b, channel 6 input comp3b i comparator input 3b aio14 i/o digital aio 14 adcinb5 33 26 i adc group b, channel 5 input adcinb4 32 25 i adc group b, channel 4 input comp2b i comparator input 2b aio12 i/o digital aio12 adcinb3 31 ? i adc group b, channel 3 input adcinb2 30 24 i adc group b, channel 2 input comp1b i comparator input 1b aio10 i/o digital aio 10 adcinb1 29 23 i adc group b, channel 1 input adcinb0 28 22 i adc group b, channel 0 input v reflo 27 21 adc external reference low. note: v reflo is always connected to v ssa on the 80-pin pn and pfp devices. cpu and i/o power v dda 25 20 analog power pin. tie with a 2.2- f capacitor (typical) close to the pin. v ssa 26 21 analog ground pin. note: v reflo is always connected to v ssa on the 80-pin pn and pfp devices. v dd 3 2 cpu and logic digital power pins. when using internal vreg, place one 1.2- f capacitor between each v dd pin and ground. higher value capacitors may be used. 14 12 37 29 63 51 81 65 91 72 v ddio 5 4 digital i/o and flash power pin. single supply source when vreg is enabled. place a 2.2-uf decoupling capacitor on each pin. the exact value of the total decoupling capacitance should be determined by the system voltage regulation solution. 13 11 38 30 61 49 79 63 93 74 v ss 4 3 digital ground pins 15 13 36 28 47 38 62 50 80 64 92 73
14 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 terminal configuration and functions copyright ? 2010 ? 2016, texas instruments incorporated table 4-1. signal descriptions (1) (continued) pin name pin no. i/o/z description pz pzp pn pfp voltage regulator control signal vregenz 90 71 i internal vreg enable/disable. pull low to enable vreg, pull high to disable vreg. gpio and peripheral signals (2) gpio0 87 69 i/o/z general-purpose input/output 0 epwm1a o enhanced pwm1 output a and hrpwm channel gpio1 86 68 i/o/z general-purpose input/output 1 epwm1b o enhanced pwm1 output b comp1out o direct output of comparator 1 gpio2 84 67 i/o/z general-purpose input/output 2 epwm2a o enhanced pwm2 output a and hrpwm channel gpio3 83 66 i/o/z general-purpose input/output 3 epwm2b o enhanced pwm2 output b spisomia i/o spi-a slave out, master in comp2out o direct output of comparator 2 gpio4 9 7 i/o/z general-purpose input/output 4 epwm3a o enhanced pwm3 output a and hrpwm channel gpio5 10 8 i/o/z general-purpose input/output 5 epwm3b o enhanced pwm3 output b spisimoa i/o spi-a slave in, master out ecap1 i/o enhanced capture input/output 1 gpio6 58 46 i/o/z general-purpose input/output 6 epwm4a o enhanced pwm4 output a and hrpwm channel epwmsynci i external epwm sync pulse input epwmsynco o external epwm sync pulse output gpio7 57 45 i/o/z general-purpose input/output 7 epwm4b o enhanced pwm4 output b scirxda i sci-a receive data ecap2 i/o enhanced capture input/output 2 gpio8 54 43 i/o/z general-purpose input/output 8 epwm5a o enhanced pwm5 output a and hrpwm channel reserved ? reserved adcsocao o adc start-of-conversion a gpio9 49 39 i/o/z general-purpose input/output 9 epwm5b o enhanced pwm5 output b scitxdb o sci-b transmit data ecap3 i/o enhanced capture input/output 3 gpio10 74 60 i/o/z general-purpose input/output 10 epwm6a o enhanced pwm6 output a and hrpwm channel reserved ? reserved adcsocbo o adc start-of-conversion b gpio11 73 59 i/o/z general-purpose input/output 11 epwm6b o enhanced pwm6 output b scirxdb i sci-b receive data ecap1 i/o enhanced capture input/output 1
15 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 terminal configuration and functions copyright ? 2010 ? 2016, texas instruments incorporated table 4-1. signal descriptions (1) (continued) pin name pin no. i/o/z description pz pzp pn pfp gpio12 44 35 i/o/z general-purpose input/output 12 tz1 i trip zone input 1 scitxda o sci-a transmit data spisimob i/o spi-b slave in, master out gpio13 95 75 i/o/z general-purpose input/output 13 tz2 i trip zone input 2 reserved ? reserved spisomib i/o spi-b slave out, master in gpio14 96 76 i/o/z general-purpose input/output 14 tz3 i trip zone input 3 scitxdb o sci-b transmit data spiclkb i/o spi-b clock input/output gpio15 88 70 i/o/z general-purpose input/output 15 ecap2 i/o enhanced capture input/output 2 scirxdb i sci-b receive data spisteb i/o spi-b slave transmit enable input/output gpio16 55 44 i/o/z general-purpose input/output 16 spisimoa i/o spi-a slave in, master out reserved ? reserved tz2 i trip zone input 2 gpio17 52 42 i/o/z general-purpose input/output 17 spisomia i/o spi-a slave out, master in reserved ? reserved tz3 i trip zone input 3 gpio18 51 41 i/o/z general-purpose input/output 18 spiclka i/o spi-a clock input/output scitxdb o sci-b transmit data xclkout o/z output clock derived from sysclkout. xclkout is either the same frequency, one- half the frequency, or one-fourth the frequency of sysclkout. this is controlled by bits 1:0 (xclkoutdiv) in the xclk register. at reset, xclkout = sysclkout/4. the xclkout signal can be turned off by setting xclkoutdiv to 3. the mux control for gpio18 must also be set to xclkout for this signal to propogate to the pin. gpio19 64 52 i/o/z general-purpose input/output 19 xclkin i external oscillator input. the path from this pin to the clock block is not gated by the mux function of this pin. care must be taken not to enable this path for clocking if it is being used for the other peripheral functions. spistea i/o spi-a slave transmit enable input/output scirxdb i sci-b receive data ecap1 i/o enhanced capture input/output 1 gpio20 6 5 i/o/z general-purpose input/output 20 eqep1a i enhanced qep1 input a mdxa o mcbsp transmit serial data comp1out o direct output of comparator 1 gpio21 7 6 i/o/z general-purpose input/output 21 eqep1b i enhanced qep1 input b mdra i mcbsp receive serial data comp2out o direct output of comparator 2
16 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 terminal configuration and functions copyright ? 2010 ? 2016, texas instruments incorporated table 4-1. signal descriptions (1) (continued) pin name pin no. i/o/z description pz pzp pn pfp gpio22 98 78 i/o/z general-purpose input/output 22 eqep1s i/o enhanced qep1 strobe mclkxa i/o mcbsp transmit clock scitxdb o sci-b transmit data gpio23 2 1 i/o/z general-purpose input/output 23 eqep1i i/o enhanced qep1 index mfsxa i/o mcbsp transmit frame synch scirxdb i sci-b receive data gpio24 97 77 i/o/z general-purpose input/output 24 ecap1 i/o enhanced capture input/output 1 eqep2a i enhanced qep2 input a. note: eqep2 is only available in the pz and pzp packages. spisimob i/o spi-b slave in, master out gpio25 39 31 i/o/z general-purpose input/output 25 ecap2 i/o enhanced capture input/output 2 eqep2b i enhanced qep2 input b. note: eqep2 is only available in the pz and pzp packages. spisomib i/o spi-b slave out, master in gpio26 78 62 i/o/z general-purpose input/output 26 ecap3 i/o enhanced capture input/output 3 eqep2i i/o enhanced qep2 index. note: eqep2 is only available in the pz and pzp packages. spiclkb i/o spi-b clock input/output usb0dp (3) i/o positive differential half of usb signal. to enable usb functionality on this pin, set the usbioen bit in the gpactrl2 register. gpio27 77 61 i/o/z general-purpose input/output 27 hrcap2 i high-resolution input capture 2 eqep2s i/o enhanced qep2 strobe. note: eqep2 is only available in the pz and pzp packages. spisteb i/o spi-b slave transmit enable input/output usb0dm (3) i/o negative differential half of usb signal. to enable usb functionality on this pin, set the usbioen bit in the gpactrl2 register. gpio28 50 40 i/o/z general-purpose input/output 28 scirxda i sci-a receive data sdaa i/od i 2 c data open-drain bidirectional port tz2 i trip zone input 2 gpio29 43 34 i/o/z general-purpose input/output 29 scitxda o sci-a transmit data scla i/od i 2 c clock open-drain bidirectional port tz3 i trip zone input 3 gpio30 41 33 i/o/z general-purpose input/output 30 canrxa i can receive eqep2i i/o enhanced qep2 index. note: eqep2 is only available in the pz and pzp packages. epwm7a o enhanced pwm7 output a and hrpwm channel
17 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 terminal configuration and functions copyright ? 2010 ? 2016, texas instruments incorporated table 4-1. signal descriptions (1) (continued) pin name pin no. i/o/z description pz pzp pn pfp gpio31 40 32 i/o/z general-purpose input/output 31 cantxa o can transmit eqep2s i/o enhanced qep2 strobe. note: eqep2 is only available in the pz and pzp packages. epwm8a o enhanced pwm8 output a and hrpwm channel gpio32 99 79 i/o/z general-purpose input/output 32 sdaa i/od i 2 c data open-drain bidirectional port epwmsynci i enhanced pwm external sync pulse input adcsocao o adc start-of-conversion a gpio33 100 80 i/o/z general-purpose input/output 33 scla i/od i 2 c clock open-drain bidirectional port epwmsynco o enhanced pwm external synch pulse output adcsocbo o adc start-of-conversion b gpio34 68 55 i/o/z general-purpose input/output 34 comp2out o direct output of comparator 2 comp3out o direct output of comparator 3 gpio35 71 57 i/o/z general-purpose input/output 35 tdi i jtag test data input (tdi) with internal pullup. tdi is clocked into the selected register (instruction or data) on a rising edge of tck. gpio36 72 58 i/o/z general-purpose input/output 36 tms i jtag test-mode select (tms) with internal pullup. this serial control input is clocked into the tap controller on the rising edge of tck. gpio37 70 56 i/o/z general-purpose input/output 37 tdo o/z jtag scan out, test data output (tdo). the contents of the selected register (instruction or data) are shifted out of tdo on the falling edge of tck (8 ma drive). gpio38 67 54 i/o/z general-purpose input/output 38 xclkin i external oscillator input. the path from this pin to the clock block is not gated by the mux function of this pin. care must be taken to not enable this path for clocking if it is being used for the other functions. tck i jtag test clock with internal pullup gpio39 66 53 i/o/z general-purpose input/output 39 gpio40 82 ? i/o/z general-purpose input/output 40 epwm7a o enhanced pwm7 output a and hrpwm channel scitxdb o sci-b transmit data gpio41 76 ? i/o/z general-purpose input/output 41 epwm7b o enhanced pwm7 output b scirxdb i sci-b receive data gpio42 1 ? i/o/z general-purpose input/output 42 epwm8a o enhanced pwm8 output a and hrpwm channel tz1 i trip zone input 1 comp1out o direct output of comparator 1 gpio43 8 ? i/o/z general-purpose input/output 43 epwm8b o enhanced pwm8 output b tz2 i trip zone input 2 comp2out o direct output of comparator 2
18 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 terminal configuration and functions copyright ? 2010 ? 2016, texas instruments incorporated table 4-1. signal descriptions (1) (continued) pin name pin no. i/o/z description pz pzp pn pfp gpio44 56 ? i/o/z general-purpose input/output 44 mfsra i/o mcbsp receive frame synch scirxdb i sci-b receive data epwm7b o enhanced pwm7 output b gpio50 42 ? i/o/z general-purpose input/output 50 eqep1a i enhanced qep1 input a mdxa o mcbsp transmit serial data tz1 i trip zone input 1 gpio51 48 ? i/o/z general-purpose input/output 51 eqep1b i enhanced qep1 input b mdra i mcbsp receive serial data tz2 i trip zone input 2 gpio52 53 ? i/o/z general-purpose input/output 52 eqep1s i/o enhanced qep1 strobe mclkxa i/o mcbsp transmit clock tz3 i trip zone input 3 gpio53 65 ? i/o/z general-purpose input/output 53 eqep1i i/o enhanced qep1 index mfsxa i/o mcbsp transmit frame synch gpio54 69 ? i/o/z general-purpose input/output 54 spisimoa i/o spi-a slave in, master out eqep2a i enhanced qep2 input a hrcap1 i high-resolution input capture 1 gpio55 75 ? i/o/z general-purpose input/output 55 spisomia i/o spi-a slave out, master in eqep2b i enhanced qep2 input b hrcap2 i high-resolution input capture 2 gpio56 85 ? i/o/z general-purpose input/output 56 spiclka i/o spi-a clock input/output eqep2i i/o enhanced qep2 index hrcap3 i high-resolution input capture 3 gpio57 89 ? i/o/z general-purpose input/output 57 spistea i/o spi-a slave transmit enable input/output eqep2s i/o enhanced qep2 strobe hrcap4 i high-resolution input capture 4 gpio58 94 ? i/o/z general-purpose input/output 58 mclkra i/o mcbsp receive clock scitxdb o sci-b transmit data epwm7a o enhanced pwm7 output a and hrpwm channel (1) i = input, o = output, z = high impedance, od = open drain, = pullup, = pulldown (2) the gpio function (shown in bold italics) is the default at reset. the peripheral signals that are listed under them are alternate functions. for jtag pins that have the gpio functionality multiplexed, the input path to the gpio block is always valid. the output path from the gpio block and the path to the jtag block from a pin is enabled or disabled based on the condition of the trst signal. see the systems control and interrupts chapter of the tms320x2806x piccolo technical reference manual ( spruh18 ). (3) depending on your usb application, additional pins may be required to maintain compliance with the usb 2.0 specification. for more information, see the universal serial bus (usb) controller chapter of the tms320x2806x piccolo technical reference manual ( spruh18 ).
19 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under section 5.4 is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to v ss , unless otherwise noted. (3) continuous clamp current per pin is 2 ma. (4) long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life. for additional information, see the ic package thermal metrics application report ( spra953 ). 5 specifications 5.1 absolute maximum ratings (1) (2) over operating free-air temperature range (unless otherwise noted) min max unit supply voltage v ddio (i/o and flash) with respect to v ss ? 0.3 4.6 v v dd with respect to v ss ? 0.3 2.5 analog voltage v dda with respect to v ssa ? 0.3 4.6 v input voltage v in (3.3 v) ? 0.3 4.6 v v in (x1) ? 0.3 2.5 output voltage v o ? 0.3 4.6 v input clamp current i ik (v in < 0 or v in > v ddio ) (3) ? 20 20 ma output clamp current i ok (v o < 0 or v o > v ddio ) ? 20 20 ma junction temperature (4) t j ? 40 150 c storage temperature (4) t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 5.2 esd ratings for tms320f2806xu value unit v (esd) electrostatic discharge (esd) human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22- c101 (2) 500 (1) aec q100-002 indicates hbm stressing is done in accordance with the ansi/esda/jedec js-001 specification. 5.3 esd ratings for tms320f2806x, tms320f2806xm, and tms320f2806xf value unit tms320f2806x, tms320f2806xm, and tms320f2806xf in 100-pin pz and pzp packages v (esd) electrostatic discharge human body model (hbm), per aec q100-002 (1) all pins 2000 v charged device model (cdm), per aec q100-011 all pins 500 corner pins on 100-pin pz and pzp: 1, 25, 26, 50, 51, 75, 76, 100 750 tms320f2806x, tms320f2806xm, and tms320f2806xf in 80-pin pn and pfp packages v (esd) electrostatic discharge human body model (hbm), per aec q100-002 (1) all pins 2000 v charged device model (cdm), per aec q100-011 all pins 500 corner pins on 80-pin pn and pfp: 1, 20, 21, 40, 41, 60, 61, 80 750
20 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated (1) group 2 pins are as follows: gpio16, gpio17, gpio18, gpio19, gpio28, gpio29, gpio36, gpio37. (2) the " q " temperature option is not available on the 2806x u devices. 5.4 recommended operating conditions min nom max unit device supply voltage, i/o, v ddio 2.97 3.3 3.63 v device supply voltage cpu, v dd (when internal vreg is disabled and 1.8 v is supplied externally) 1.71 1.8 1.995 v supply ground, v ss 0 v analog supply voltage, v dda 2.97 3.3 3.63 v analog ground, v ssa 0 v device clock frequency (system clock) 2 90 mhz high-level input voltage, v ih (3.3 v) 2 v ddio + 0.3 v low-level input voltage, v il (3.3 v) v ss ? 0.3 0.8 v high-level output source current, v oh = v oh(min) , i oh all gpio/aio pins ? 4 ma group 2 (1) ? 8 low-level output sink current, v ol = v ol(max) , i ol all gpio/aio pins 4 ma group 2 (1) 8 junction temperature, t j t version ? 40 105 c s version ? 40 125 ambient temperature, t a q version (2) (q100 qualification) ? 40 125 c (1) when the on-chip vreg is used, its output is monitored by the por/bor circuit, which will reset the device should the core voltage (v dd ) go out of range. 5.5 electrical characteristics (1) over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage i oh = i oh max 2.4 v i oh = 50 a v ddio ? 0.2 v ol low-level output voltage i ol = i ol max 0.4 v i il input current (low level) pin with pullup enabled v ddio = 3.3 v, v in = 0 v all gpio ? 80 ? 140 ? 205 a xrs pin ? 230 ? 300 ? 375 pin with pulldown enabled v ddio = 3.3 v, v in = 0 v 2 i ih input current (high level) pin with pullup enabled v ddio = 3.3 v, v in = v ddio 2 a pin with pulldown enabled v ddio = 3.3 v, v in = v ddio 28 50 80 i oz output current, pullup or pulldown disabled v o = v ddio or 0 v 2 a c i input capacitance 2 pf v ddio bor trip point falling v ddio 2.50 2.78 2.96 v v ddio bor hysteresis 35 mv supervisor reset release delay time time after bor/por/ovr event is removed to xrs release 400 800 s vreg v dd output internal vreg on 1.9 v
21 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated (1) i ddio current is dependent on the electrical loading on the i/o pins. (2) in order to realize the i dda currents shown for idle, standby, and halt, clock to the adc module must be turned off explicitly by writing to the pclkcr0 register. (3) the typ numbers are applicable over room temperature and nominal voltage. (4) the following is done in a loop: ? data is continuously transmitted out of spi-a, spi-b, sci-a, ecan-a, mcbsp-a, and i 2 c ports. ? the hardware multiplier is exercised. ? watchdog is reset. ? adc is performing continuous conversion. ? comp1 and comp2 are continuously switching voltages. ? gpio17 is toggled. (5) cla is continuously performing polynomial calculations. (6) for f2806x devices that do not have cla, subtract the i dd current number for cla (see table 5-2 ) from the i dd (vreg disabled)/i ddio (vreg enabled) current numbers shown in table 5-1 for operational mode. (7) if a quartz crystal or ceramic resonator is used as the clock source, the halt mode shuts down the on-chip crystal oscillator. (8) to realize the i dd number shown for halt mode, the following must be done: ? pll2 must be shut down by clearing bit 2 of the pllctl register. ? a value of 0x00ff must be written to address 0x6822. 5.6 power consumption summary table 5-1. tms320f2806x current consumption at 90-mhz sysclkout mode test conditions vreg enabled vreg disabled i ddio (1) i dda (2) i dd3vfl i dd i ddio (1) i dda (2) i dd3vfl typ (3) max typ (3) max typ (3) max typ (3) max typ (3) max typ (3) max typ (3) max operational (flash) the following peripheral clocks are enabled: ? epwm1, epwm2, epwm3, epwm4, epwm5, epwm6, epwm7, epwm8 ? ecap1, ecap2, ecap3 ? eqep1, eqep2 ? ecan ? cla ? hrpwm ? sci-a, sci-b ? spi-a, spi-b ? adc ? i 2 c ? comp1, comp2, comp3 ? cpu-timer0, cpu-timer1, cpu-timer2 ? mcbsp ? usb all pwm pins are toggled at 90 khz. all i/o pins are left unconnected. (4) (5) code is running out of flash with 3 wait-states. xclkout is turned off. 185 ma (6) 245 ma (6) 16 ma 22 ma 35 ma 40 ma 165 ma (6) 220 ma (6) 15 ma 20 ma 16 ma 22 ma 35 ma 40 ma idle flash is powered down. xclkout is turned off. all peripheral clocks are turned off. 22 ma 27 ma 15 a 25 a 5 a 10 a 21 ma 26 ma 120 a 400 a 15 a 25 a 5 a 10 a standby flash is powered down. peripheral clocks are off. 9 ma 11 ma 15 a 25 a 5 a 10 a 8 ma 10 ma 120 a 400 a 15 a 25 a 5 a 10 a halt flash is powered down. peripheral clocks are off. input clock is disabled. (7) 75 a 15 a 25 a 5 a 10 a 25 a (8) 40 a 15 a 25 a 5 a 10 a
22 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated note the peripheral - i/o multiplexing implemented in the device prevents all available peripherals from being used at the same time. this is because more than one peripheral function may share an i/o pin. it is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. if this is done, the current drawn by the device will be more than the numbers specified in the current consumption tables.
23 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated 5.6.1 reducing current consumption the 2806x devices incorporate a method to reduce the device current consumption. since each peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning off the clock to any peripheral module that is not used in a given application. furthermore, any one of the three low-power modes could be taken advantage of to reduce the current consumption even further. table 5-2 indicates the typical reduction in current consumption achieved by turning off the clocks. (1) all peripheral clocks (except cpu timer clock) are disabled upon reset. writing to or reading from peripheral registers is possible only after the peripheral clocks are turned on. (2) for peripherals with multiple instances, the current quoted is per module. for example, the 2 ma value quoted for epwm is for one epwm module. (3) this number represents the current drawn by the digital portion of the adc module. turning off the clock to the adc module results in the elimination of the current drawn by the analog portion of the adc (i dda ) as well. table 5-2. typical current consumption by various peripherals (at 90 mhz) (1) peripheral module (2) i dd current reduction (ma) adc 2 (3) i 2 c 3 epwm 2 ecap 2 eqep 2 sci 2 spi 2 comp/dac 1 hrpwm 3 hrcap 3 usb 12 cpu-timer 1 internal zero-pin oscillator 0.5 can 2.5 cla 20 mcbsp 6 note i ddio current consumption is reduced by 15 ma (typical) when xclkout is turned off. note the baseline i dd current (current when the core is executing a dummy loop with no peripherals enabled) is 40 ma, typical. to arrive at the i dd current for a given application, the current-drawn by the peripherals (enabled by that application) must be added to the baseline i dd current.
24 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated following are other methods to reduce power consumption further: ? the flash module may be powered down if code is run off saram. this results in a current reduction of 18 ma (typical) in the v dd rail and 13 ma (typical) in the v ddio rail. ? savings in i ddio may be realized by disabling the pullups on pins that assume an output function. 5.6.2 current consumption graphs (vreg enabled) figure 5-1. typical operational current versus frequency figure 5-2. typical operational power versus frequency 0 50 100 150 200 250 10 20 30 40 50 60 70 80 90 operational current (ma) sysclkout (mhz) operational current (flash) vs frequency (internal vreg) iddio idda idd3vfl total 0 100 200 300 400 500 600 700 800 900 10 20 30 40 50 60 70 80 90 operational power (mw) sysclkout (mhz) operational power vs frequency (internal vreg)
25 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated (1) these values are based on a jedec-defined 2s2p system (with the exception of the theta jc [r jc ] value, which is based on a jedec-defined 1s0p system) and will change based on environment as well as application. for more information, see these eia/jedec standards: ? jesd51-2, integrated circuits thermal test method environmental conditions - natural convection (still air) ? jesd51-3, low effective thermal conductivity test board for leaded surface mount packages ? jesd51-7, high effective thermal conductivity test board for leaded surface mount packages ? jesd51-9, test boards for area array surface mount package thermal measurements (2) lfm = linear feet per minute 5.7 thermal resistance characteristics 5.7.1 pfp powerpad package c/w (1) air flow (lfm) (2) r jc junction-to-case thermal resistance 9.4 0 r jb junction-to-board thermal resistance 4.6 0 r ja (high k pcb) junction-to-free air thermal resistance 25.8 0 16.3 150 15.2 250 13.6 500 psi jt junction-to-package top 0.3 0 0.4 150 0.4 250 0.5 500 psi jb junction-to-board 4.6 0 4.4 150 4.3 250 4.3 500 (1) these values are based on a jedec-defined 2s2p system (with the exception of the theta jc [r jc ] value, which is based on a jedec-defined 1s0p system) and will change based on environment as well as application. for more information, see these eia/jedec standards: ? jesd51-2, integrated circuits thermal test method environmental conditions - natural convection (still air) ? jesd51-3, low effective thermal conductivity test board for leaded surface mount packages ? jesd51-7, high effective thermal conductivity test board for leaded surface mount packages ? jesd51-9, test boards for area array surface mount package thermal measurements (2) lfm = linear feet per minute 5.7.2 pzp powerpad package c/w (1) air flow (lfm) (2) r jc junction-to-case thermal resistance 9.4 0 r jb junction-to-board thermal resistance 4.4 0 r ja (high k pcb) junction-to-free air thermal resistance 24.4 0 15.1 150 13.9 250 12.4 500 psi jt junction-to-package top 0.3 0 0.4 150 0.4 250 0.5 500 psi jb junction-to-board 4.5 0 4.2 150 4.2 250 4.2 500
26 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated (1) these values are based on a jedec-defined 2s2p system (with the exception of the theta jc [r jc ] value, which is based on a jedec-defined 1s0p system) and will change based on environment as well as application. for more information, see these eia/jedec standards: ? jesd51-2, integrated circuits thermal test method environmental conditions - natural convection (still air) ? jesd51-3, low effective thermal conductivity test board for leaded surface mount packages ? jesd51-7, high effective thermal conductivity test board for leaded surface mount packages ? jesd51-9, test boards for area array surface mount package thermal measurements (2) lfm = linear feet per minute 5.7.3 pn package c/w (1) air flow (lfm) (2) r jc junction-to-case thermal resistance 7.9 0 r jb junction-to-board thermal resistance 15.6 0 r ja (high k pcb) junction-to-free air thermal resistance 41.1 0 31.2 150 29.7 250 27.5 500 psi jt junction-to-package top 0.4 0 0.6 150 0.7 250 0.9 500 psi jb junction-to-board 15.3 0 14.6 150 14.4 250 14.1 500 (1) these values are based on a jedec-defined 2s2p system (with the exception of the theta jc [r jc ] value, which is based on a jedec-defined 1s0p system) and will change based on environment as well as application. for more information, see these eia/jedec standards: ? jesd51-2, integrated circuits thermal test method environmental conditions - natural convection (still air) ? jesd51-3, low effective thermal conductivity test board for leaded surface mount packages ? jesd51-7, high effective thermal conductivity test board for leaded surface mount packages ? jesd51-9, test boards for area array surface mount package thermal measurements (2) lfm = linear feet per minute 5.7.4 pz package c/w (1) air flow (lfm) (2) r jc junction-to-case thermal resistance 7.2 0 r jb junction-to-board thermal resistance 19.6 0 r ja (high k pcb) junction-to-free air thermal resistance 42.2 0 32.4 150 30.9 250 28.7 500 psi jt junction-to-package top 0.4 0 0.6 150 0.7 250 0.9 500 psi jb junction-to-board 19.1 0 18.2 150 17.9 250 14.1 500
27 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated 5.8 thermal design considerations based on the end application design and operational profile, the i dd and i ddio currents could vary. systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. ambient temperature (t a ) varies with the end application and product design. the critical factor that affects reliability and functionality is t j , the junction temperature, not the ambient temperature. hence, care should be taken to keep t j within the specified limits. t case should be measured to estimate the operating junction temperature t j . t case is normally measured at the center of the package top-side surface. the thermal application report ic package thermal metrics ( spra953 ) helps to understand the thermal metrics and definitions. 5.9 emulator connection without signal buffering for the mcu figure 5-3 shows the connection between the mcu and jtag header for a single-processor configuration. if the distance between the jtag header and the mcu is greater than 6 inches, the emulation signals must be buffered. if the distance is less than 6 inches, buffering is typically not needed. figure 5-3 shows the simpler, no-buffering situation. for the pullup and pulldown resistor values, see section 4.2 . a. see figure 6-54 for jtag/gpio multiplexing. figure 5-3. emulator connection without signal buffering for the mcu note the 2806x devices do not have emu0/emu1 pins. for designs that have a jtag header onboard, the emu0/emu1 pins on the header must be tied to v ddio through a 4.7-k ? (typical) resistor. trst tms tdi tdo tck v ddio mcu emu0emu1 trst tmstdi tdo tck tck_ret 1314 21 3 7 11 9 6 inches or less pd gnd gndgnd gnd gnd 54 6 8 10 12 jtag header v ddio
28 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated 5.10 parameter information 5.10.1 timing parameter symbology timing parameter symbols used are created in accordance with jedec standard 100. to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: lowercase subscripts and their meanings: letters and symbols and their meanings: a access time h high c cycle time (period) l low d delay time v valid f fall time x unknown, changing, or don't care level h hold time z high impedance r rise time su setup time t transition time v valid time w pulse duration (width) 5.10.2 general notes on timing parameters all output signals from the 28x devices (including xclkout) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. the signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. for actual cycle examples, see the appropriate cycle description section of this document. 5.11 test load circuit this test load circuit is used to measure all switching characteristics provided in this document. a. input requirements in this data sheet are tested with an input slew rate of < 4 volts per nanosecond (4 v/ns) at the device pin. b. the data sheet provides timing at the device pin. for output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. a transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. the transmission line is intended as a load only. it is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing. figure 5-4. 3.3-v test load circuit transmission line 4.0 pf 1.85 pf z0 = 50 w (a) tester pin electronics data sheet timing reference point outputunder test 42 w 3.5 nh device pin (b)
29 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated 5.12 power sequencing there is no power sequencing requirement needed to ensure the device is in the proper state after reset or to prevent the i/os from glitching during power up or power down (gpio19, gpio26 ? 27, gpio34 ? 38 do not have glitch-free i/os). no voltage larger than a diode drop (0.7 v) above v ddio should be applied to any digital pin before powering up the device. voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results. a. upon power up, sysclkout is oscclk/4. since the xclkoutdiv bits in the xclk register come up with a reset state of 0, sysclkout is further divided by 4 before it appears at xclkout. xclkout = oscclk/16 during this phase. b. boot rom configures the divsel bits for /1 operation. xclkout = oscclk/4 during this phase. note that xclkout will not be visible at the pin until explicitly configured by user code. c. after reset, the boot rom code samples boot mode pins. based on the status of the boot mode pin, the boot code branches to destination memory or boot code function. if boot rom code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current sysclkout speed. the sysclkout will be based on user environment and could be with or without pll enabled. d. using the xrs pin is optional due to the on-chip por circuitry. e. the internal pullup or pulldown will take effect when bor is driven high. figure 5-5. power-on reset t w(rsl1) t h(boot-mode) (c) v v (3.3 v) ddio dda , intosc1 x1/x2 xrs (d) boot-mode pins v (1.8 v) dd xclkout user-code dependent user-code dependent boot-rom execution starts peripheral/gpio functionbased on boot code gpio pins as input t oscst address/data/ control (internal) address/data valid, internal boot-rom code execution phase user-code execution phase t d(ex) t intoscst (a) (b) i/o pins gpio pins as input [state depends on internal pullup/pulldown (pu/pd)] user-code dependent (e)
30 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated table 5-3. reset ( xrs ) timing requirements min max unit t h(boot-mode) hold time for boot-mode pins 1000t c(sco) cycles t w(rsl2) pulse duration, xrs low on warm reset 32t c(oscclk) cycles (1) dependent on crystal/resonator and board design. table 5-4. reset ( xrs ) switching characteristics over recommended operating conditions (unless otherwise noted) parameter min typ max unit t w(rsl1) pulse duration, xrs driven by device 600 s t w(wdrs) pulse duration, reset pulse generated by watchdog 512t c(oscclk) cycles t d(ex) delay time, address/data valid after xrs high 32t c(oscclk) cycles t intoscst start up time, internal zero-pin oscillator 3 s t oscst (1) on-chip crystal-oscillator start-up time 1 10 ms a. after reset, the boot rom code samples boot mode pins. based on the status of the boot mode pin, the boot code branches to destination memory or boot code function. if boot rom code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current sysclkout speed. the sysclkout will be based on user environment and could be with or without pll enabled. figure 5-6. warm reset t h(boot-mode) (a) t w(rsl2) intosc1 x1/x2 xrs boot-mode pins xclkout i/o pins address/data/ control (internal) boot-rom execution starts user-code execution starts user-code dependent user-code execution phase user-code dependent user-code execution peripheral/gpio function user-code dependent gpio pins as input (state depends on internal pu/pd) gpio pins as input peripheral/gpio function t d(ex)
31 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated figure 5-7 shows an example for the effect of writing into pllcr register. in the first phase, pllcr = 0x0004 and sysclkout = oscclk 2. the pllcr is then written with 0x0008. right after the pllcr register is written, the pll lock-up phase begins. during this phase, sysclkout = oscclk/2. after the pll lock-up is complete, sysclkout reflects the new operating frequency, oscclk 4. figure 5-7. example of effect of writing into pllcr register oscclk sysclkout write to pllcr oscclk * 2 (current cpu frequency) oscclk/2 (cpu frequency while pll is stabilizing with the desired frequency. this period (pll lock-up time t ) is 1 ms long.) p oscclk * 4 (changed cpu frequency)
32 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated (1) lower lspclk will reduce device power consumption. (2) this is the default reset value if sysclkout = 90 mhz. 5.13 clock specifications 5.13.1 device clock table this section provides the timing requirements and switching characteristics for the various clock options available on the 2806x mcus. table 5-5 lists the cycle times of various clocks. table 5-5. 2806x clock table and nomenclature (90-mhz devices) min nom max unit sysclkout t c(sco) , cycle time 11.11 500 ns frequency 2 90 mhz lspclk (1) t c(lco) , cycle time 11.11 44.4 (2) ns frequency 22.5 (2) 90 mhz adc clock t c(adcclk) , cycle time 22.22 ns frequency 45 mhz (1) the plllockprd register must be updated based on the number of oscclk cycles. if the zero-pin internal oscillators (10 mhz) are used as the clock source, then the plllockprd register must be written with a value of 10,000 (minimum). table 5-6. device clocking requirements/characteristics min nom max unit on-chip oscillator (x1/x2 pins) (crystal/resonator) t c(osc) , cycle time 50 200 ns frequency 5 20 mhz external oscillator/clock source (xclkin pin) ? pll enabled t c(ci) , cycle time (c8) 33.3 200 ns frequency 5 30 mhz external oscillator/clock source (xclkin pin) ? pll disabled t c(ci) , cycle time (c8) 11.11 250 ns frequency 4 90 mhz limp mode sysclkout (with /2 enabled) frequency range 1 to 5 mhz xclkout t c(xco) , cycle time (c1) 44.44 2000 ns frequency 0.5 22.5 mhz pll lock time (1) t p 1 ms
33 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated (1) in order to achieve better oscillator accuracy (10 mhz 1% or better) than shown, refer to the oscillator compensation guide application report ( sprab84 ). (2) frequency range ensured only when vreg is enabled, vregenz = v ss . (3) output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (v dd ) gradient. for example: ? increase in temperature will cause the output frequency to increase per the temperature coefficient. ? decrease in voltage (v dd ) will cause the output frequency to decrease per the voltage coefficient. table 5-7. internal zero-pin oscillator (intosc1/intosc2) characteristics parameter min typ max unit internal zero-pin oscillator 1 (intosc1) at 30 c (1) (2) frequency 10.000 mhz internal zero-pin oscillator 2 (intosc2) at 30 c (1) (2) frequency 10.000 mhz step size (coarse trim) 55 khz step size (fine trim) 14 khz temperature drift (3) 3.03 4.85 khz/ c voltage (v dd ) drift (3) 175 hz/mv figure 5-8. zero-pin oscillator frequency movement with temperature zero-pin oscillator frequency movement with temperature 9.6 9.7 9.8 9.9 10 10.1 10.2 10.3 10.4 10.5 10.6 C40 C30 C20 C10 0 10 20 30 40 50 60 70 80 90 100 110 120 temperature (c) output frequency (mhz) typical max
34 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated 5.13.2 clock requirements and characteristics table 5-8. xclkin timing requirements - pll enabled no. min max unit c9 t f(ci) fall time, xclkin 6 ns c10 t r(ci) rise time, xclkin 6 ns c11 t w(cil) pulse duration, xclkin low as a percentage of t c(oscclk) 45% 55% c12 t w(cih) pulse duration, xclkin high as a percentage of t c(oscclk) 45% 55% table 5-9. xclkin timing requirements - pll disabled no. min max unit c9 t f(ci) fall time, xclkin up to 20 mhz 6 ns 20 mhz to 90 mhz 2 c10 t r(ci) rise time, xclkin up to 20 mhz 6 ns 20 mhz to 90 mhz 2 c11 t w(cil) pulse duration, xclkin low as a percentage of t c(oscclk) 45% 55% c12 t w(cih) pulse duration, xclkin high as a percentage of t c(oscclk) 45% 55% (1) a load of 40 pf is assumed for these parameters. (2) h = 0.5t c(xco) the possible configuration modes are shown in table 6-15 . table 5-10. xclkout switching characteristics (pll bypassed or enabled) (1) (2) over recommended operating conditions (unless otherwise noted) no. parameter min max unit c3 t f(xco) fall time, xclkout 5 ns c4 t r(xco) rise time, xclkout 5 ns c5 t w(xcol) pulse duration, xclkout low h ? 2 h + 2 ns c6 t w(xcoh) pulse duration, xclkout high h ? 2 h + 2 ns a. the relationship of xclkin to xclkout depends on the divide factor chosen. the waveform relationship shown is intended to illustrate the timing parameters only and may differ based on actual configuration. b. xclkout configured to reflect sysclkout. figure 5-9. clock timing c4 c3 xclkout (b) xclkin (a) c5 c9 c10 c1 c8 c6
35 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated (1) write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. 5.14 flash timing table 5-11. flash/otp endurance for t temperature material (1) erase/program temperature min typ max unit n f flash endurance for the array (write/erase cycles) 0 c to 105 c (ambient) 20000 50000 cycles n otp otp endurance for the array (write cycles) 0 c to 30 c (ambient) 1 write (1) write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. table 5-12. flash/otp endurance for s temperature material (1) erase/program temperature min typ max unit n f flash endurance for the array (write/erase cycles) 0 c to 125 c (ambient) 20000 50000 cycles n otp otp endurance for the array (write cycles) 0 c to 30 c (ambient) 1 write (1) write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. (2) the " q " temperature option is not available on the 2806x u devices. table 5-13. flash/otp endurance for q temperature material (1) (2) erase/program temperature min typ max unit n f flash endurance for the array (write/erase cycles) ? 40 c to 125 c (ambient) 20000 50000 cycles n otp otp endurance for the array (write cycles) ? 40 c to 30 c (ambient) 1 write (1) the on-chip flash memory is in an erased state when the device is shipped from ti. as such, erasing the flash memory is not required before programming, when programming the device for the first time. however, the erase operation is needed on all subsequent programming operations. (2) typical parameters as seen at room temperature including function call overhead, with all peripherals off. it is important to maintain a stable power supply during the entire flash programming process. it is conceivable that device current consumption during flash programming could be higher than normal operating conditions. the power supply used should ensure v min on the supply rails at all times, as specified in the recommended operating conditions of the data sheet. any brown-out or interruption to power during erasing/programming could potentially corrupt the password locations and lock the device permanently. powering a target board (during flash programming) through the usb port is not recommended, as the port may be unable to respond to the power demands placed during the programming process. table 5-14. flash parameters at 90-mhz sysclkout parameter test conditions min typ max unit program time 16-bit word 50 s 16k sector 500 ms 8k sector 250 ms 4k sector 125 ms erase time (1) 16k sector 2 s 8k sector 2 4k sector 2 i ddp (2) v dd current consumption during erase/program cycle vreg disabled 80 ma i ddiop (2) v ddio current consumption during erase/program cycle 60 i ddiop (2) v ddio current consumption during erase/program cycle vreg enabled 120 ma
36 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 specifications copyright ? 2010 ? 2016, texas instruments incorporated table 5-15. flash/otp access timing parameter min max unit t a(fp) paged flash access time 36 ns t a(fr) random flash access time 36 ns t a(otp) otp access time 60 ns table 5-16. flash data retention duration parameter test conditions min max unit t retention data retention duration t j = 55 c 15 years (1) page and random wait-state must be 1. table 5-17. minimum required flash/otp wait-states at different frequencies sysclkout (mhz) sysclkout (ns) page wait-state (1) random wait-state (1) otp wait-state 90 11.11 3 3 5 80 12.5 2 2 4 70 14.29 2 2 4 60 16.67 2 2 3 55 18.18 1 1 3 50 20 1 1 2 45 22.22 1 1 2 40 25 1 1 2 35 28.57 1 1 2 30 33.33 1 1 1 the equations to compute the flash page wait-state and random wait-state in table 5-17 are as follows: the equation to compute the otp wait-state in table 5-17 is as follows: larger is whichever 1, or integer, highest next the to up round 1 state wait page flash ? ? - ? ? ? ? ? = t t c(sco) p) a(f larger is whichever 1, or integer, highest next the to up round 1 state wait random flash ? ? - ? ? ? ? ? = t t c(sco) r)a(f larger is whichever 1, or integer, highest next the to up round 1 state wait otp ? ? - ? ? ? ? ? = t t c(sco) a(otp)
37 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6 detailed description 6.1 overview 6.1.1 cpu the 2806x (c28x) family is a member of the tms320c2000 ? microcontroller (mcu) platform. the c28x- based controllers have the same 32-bit fixed-point architecture as existing c28x mcus. each c28x-based controller, including the 2806x device, is a very efficient c/c++ engine, enabling users to develop not only their system control software in a high-level language, but also enabling development of math algorithms using c/c++. the device is as efficient at mcu math tasks as it is at system control tasks that typically are handled by microcontroller devices. this efficiency removes the need for a second processor in many systems. the 32 32-bit mac 64-bit processing capabilities enable the controller to handle higher numerical resolution problems efficiently. add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. the device has an 8-level-deep protected pipeline with pipelined memory accesses. this pipelining enables it to execute at high speeds without resorting to expensive high-speed memories. special branch-look-ahead hardware minimizes the latency for conditional discontinuities. special store conditional operations further improve performance. 6.1.2 control law accelerator (cla) the c28x control law accelerator is a single-precision (32-bit) floating-point unit that extends the capabilities of the c28x cpu by adding parallel processing. the cla is an independent processor with its own bus structure, fetch mechanism, and pipeline. eight individual cla tasks, or routines, can be specified. each task is started by software or a peripheral such as the adc, epwm, ecap, eqep, or cpu timer 0. the cla executes one task at a time to completion. when a task completes the main cpu is notified by an interrupt to the pie and the cla automatically begins the next highest-priority pending task. the cla can directly access the adc result registers, epwm+hrpwm, ecap, and eqep registers. dedicated message rams provide a method to pass additional data between the main cpu and the cla.
38 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.1.3 viterbi, complex math, crc unit (vcu) the c28x vcu enhances the processing power of c2000 ? devices by adding additional assembly instructions to target complex math, viterbi decode, and crc calculations. the vcu instructions accelerate many applications, including the following: ? orthogonal frequency-division multiplex (ofdm) used in the prime and g3 standards for power line communications ? short-range radar complex math calculations ? power calculations ? memory and data communication packet checks (crc) the vcu features include: ? instructions to support cyclic redundancy checks (crcs), which is a polynomial code checksum. ? crc8 ? crc16 ? crc32 ? instructions to support a flexible software implementation of a viterbi decoder ? branch metric calculations for a code rate of 1/2 or 1/3 ? add-compare select or viterbi butterfly in 5 cycles per butterfly ? traceback in 3 cycles per stage ? easily supports a constraint length of k = 7 used in prime and g3 standards ? complex math arithmetic unit ? single-cycle add or subtract ? 2-cycle multiply ? 2-cycle multiply and accumulate (mac) ? single-cycle repeat mac ? independent register space 6.1.4 memory bus (harvard bus architecture) as with many mcu-type devices, multiple busses are used to move data between the memories and peripherals and the cpu. the memory bus architecture contains a program read bus, data read bus, and data write bus. the program read bus consists of 22 address lines and 32 data lines. the data read and write busses consist of 32 address lines and 32 data lines each. the 32-bit-wide data busses enable single cycle 32-bit operations. the multiple bus architecture, commonly termed harvard bus, enables the c28x to fetch an instruction, read a data value and write a data value in a single cycle. all peripherals and memories attached to the memory bus prioritize memory accesses. generally, the priority of memory bus accesses can be summarized as follows: highest: data writes (simultaneous data and program writes cannot occur on the memory bus.) program writes (simultaneous data and program writes cannot occur on the memory bus.) data reads program reads (simultaneous program reads and fetches cannot occur on the memory bus.) lowest: fetches (simultaneous program reads and fetches cannot occur on the memory bus.)
39 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) ieee standard 1149.1-1990 standard test access port and boundary scan architecture 6.1.5 peripheral bus to enable migration of peripherals between various texas instruments (ti) mcu family of devices, the devices adopt a peripheral bus standard for peripheral interconnect. the peripheral bus bridge multiplexes the various busses that make up the processor memory bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. three versions of the peripheral bus are supported. one version supports only 16-bit accesses (called peripheral frame 2). another version supports both 16- and 32-bit accesses (called peripheral frame 1). 6.1.6 real-time jtag and analysis the devices implement the standard ieee 1149.1 jtag (1) interface for in-circuit based debug. additionally, the devices support real-time mode of operation allowing modification of the contents of memory, peripheral, and register locations while the processor is running and executing code and servicing interrupts. the user can also single step through non-time-critical code while enabling time- critical interrupts to be serviced without interference. the device implements the real-time mode in hardware within the cpu. this is a feature unique to the 28x family of devices, requiring no software monitor. additionally, special analysis hardware is provided that allows setting of hardware breakpoint or data/address watch-points and generating various user-selectable break events when a match occurs. 6.1.7 flash the f28069, f28068, f28067, and f28066 devices contain 128k 16 of embedded flash memory, segregated into eight 16k 16 sectors. the f28065, f28064, f28063, and f28062 devices contain 64k 16 of embedded flash memory, segregated into eight 8k 16 sectors. all devices also contain a single 1k 16 of otp memory at address range 0x3d 7800 ? 0x3d 7bf9. the user can individually erase, program, and validate a flash sector while leaving other sectors untouched. however, it is not possible to use one sector of the flash or the otp to execute flash algorithms that erase or program other sectors. special memory pipelining is provided to enable the flash module to achieve higher performance. the flash/otp is mapped to both program and data space; therefore, it can be used to execute code or store data information. addresses 0x3f 7ff0 ? 0x3f 7ff5 are reserved for data variables and should not contain program code. note the flash and otp wait-states can be configured by the application. this allows applications running at slower frequencies to configure the flash to use fewer wait-states. flash effective performance can be improved by enabling the flash pipeline mode in the flash options register. with this mode enabled, effective performance of linear code execution will be much faster than the raw performance indicated by the wait-state configuration alone. the exact performance gain when using the flash pipeline mode is application-dependent. for more information on the flash options, flash wait-state, and otp wait-state registers, see the systems control and interrupts chapter of the tms320x2806x piccolo technical reference manual ( spruh18 ).
40 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.1.8 m0, m1 sarams all devices contain these two blocks of single-access memory, each 1k 16 in size. the stack pointer points to the beginning of block m1 on reset. the m0 and m1 blocks, like all other memory blocks on c28x devices, are mapped to both program and data space. hence, the user can use m0 and m1 to execute code or for data variables. the partitioning is performed within the linker. the c28x device presents a unified memory map to the programmer. this makes for easier programming in high-level languages. 6.1.9 l4 saram, and l0, l1, l2, l3, l5, l6, l7, and l8 dpsarams the device contains up to 48k 16 of single-access ram. to ascertain the exact size for a given device, see the device-specific memory map figures in section 6.2 . this block is mapped to both program and data space. l0 is 2k in size. l1 and l2 are each 1k in size. l3 is 4k in size. l4, l5, l6, l7, and l8 are each 8k in size. l0, l1, and l2 are shared with the cla, which can use these blocks for its data space. l3 is shared with the cla, which can use this block for its program space. l5, l6, l7, and l8 are shared with the dma, which can use these blocks for its data space. dpsaram refers to the dual-port configuration of these blocks. 6.1.10 boot rom the boot rom is factory-programmed with boot-loading software. boot-mode signals are provided to tell the bootloader software what boot mode to use on power up. the user can select to boot normally or to download new software from an external connection or to select boot software that is programmed in the internal flash/rom. the boot rom also contains standard tables, such as sin/cos waveforms, for use in math-related algorithms. table 6-1. boot mode selection mode gpio37/tdo gpio34/comp2out/ comp3out trst mode 3 1 1 0 getmode 2 1 0 0 wait (see section 6.1.11 for description) 1 0 1 0 sci 0 0 0 0 parallel io emu x x 1 emulation boot 6.1.10.1 emulation boot when the emulator is connected, the gpio37/tdo pin cannot be used for boot mode selection. in this case, the boot rom detects that an emulator is connected and uses the contents of two reserved saram locations in the pie vector table to determine the boot mode. if the content of either location is invalid, then the wait boot option is used. all boot mode options can be accessed in emulation boot. 6.1.10.2 getmode the default behavior of the getmode option is to boot to flash. this behavior can be changed to another boot option by programming two locations in the otp. if the content of either otp location is invalid, then boot to flash is used. one of the following loaders can be specified: sci, spi, i 2 c, can, or otp.
41 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.1.10.3 peripheral pins used by the bootloader table 6-2 shows which gpio pins are used by each peripheral bootloader. refer to the gpio mux table to see if these conflict with any of the peripherals you would like to use in your application. table 6-2. peripheral bootload pins bootloader peripheral loader pins sci scirxda (gpio28) scitxda (gpio29) parallel boot data (gpio31,30,5:0) 28x control (aio6) host control (aio12) spi spisimoa (gpio16) spisomia (gpio17) spiclka (gpio18) spistea (gpio19) i 2 c sdaa (gpio32) scla (gpio33) can canrxa (gpio30) cantxa (gpio31) 6.1.11 security the devices support high levels of security to protect the user firmware from being reverse-engineered. the security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the flash. one code security module (csm) is used to protect the flash/otp and the l0/l1 saram blocks. the security feature prevents unauthorized users from examining the memory contents through the jtag port, executing code from external memory or trying to boot-load some undesirable software that would export the secure memory contents. to enable access to the secure blocks, the user must write the correct 128-bit key value that matches the value stored in the password locations within the flash. in addition to the csm, the emulation code security logic (ecsl) has been implemented to prevent unauthorized users from stepping through secure code. any code or data access to csm secure memory while the emulator is connected will trip the ecsl and break the emulation connection. to allow emulation of secure code, while maintaining the csm protection against secure memory reads, the user must write the correct value into the lower 64 bits of the key register, which matches the value stored in the lower 64 bits of the password locations within the flash. note that dummy reads of all 128 bits of the password in the flash must still be performed. if the lower 64 bits of the password locations are all ones (unprogrammed), then the key value does not need to match. when initially debugging a device with the password locations in flash programmed (that is, secured), the cpu will start running and may execute an instruction that performs an access to a protected ecsl area. if this happens, the ecsl will trip and cause the emulator connection to be cut.
42 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated the solution is to use the wait boot option. this will sit in a loop around a software breakpoint to allow an emulator to be connected without tripping security. piccolo devices do not support a hardware wait-in- reset mode. note ? when the code-security passwords are programmed, all addresses between 0x3f 7f80 and 0x3f 7ff5 cannot be used as program code or data. these locations must be programmed to 0x0000. ? if the code security feature is not used, addresses 0x3f 7f80 through 0x3f 7fef may be used for code or data. addresses 0x3f 7ff0 ? 0x3f 7ff5 are reserved for data and should not contain program code. ? the 128-bit password (at 0x3f 7ff8 ? 0x3f 7fff) must not be programmed to zeros. doing so would permanently lock the device. disclaimer code security module disclaimer the code security module (csm) included on this device was designed to password protect the data stored in the associated memory (either rom or flash) and is warranted by texas instruments (ti), in accordance with its standard terms and conditions, to conform to ti's published specifications for the warranty period applicable for this device. ti does not, however, warrant or represent that the csm cannot be compromised or breached or that the data stored in the associated memory cannot be accessed through other means. moreover, except as set forth above, ti makes no warranties or representations concerning the csm or operation of this device, including any implied warranties of merchantability or fitness for a particular purpose. in no event shall ti be liable for any consequential, special, indirect, incidental, or punitive damages, however caused, arising in any way out of your use of the csm or this device, whether or not ti has been advised of the possibility of such damages. excluded damages include, but are not limited to loss of data, loss of goodwill, loss of use or interruption of business or other economic loss. 6.1.12 peripheral interrupt expansion (pie) block the pie block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. the pie block can support up to 96 peripheral interrupts. on the f2806x, 72 of the possible 96 interrupts are used by peripherals. the 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 cpu interrupt lines (int1 to int12). each of the 96 interrupts is supported by its own vector stored in a dedicated ram block that can be overwritten by the user. the vector is automatically fetched by the cpu on servicing the interrupt. eight cpu clock cycles are needed to fetch the vector and save critical cpu registers. hence the cpu can quickly respond to interrupt events. prioritization of interrupts is controlled in hardware and software. each individual interrupt can be enabled or disabled within the pie block.
43 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.1.13 external interrupts (xint1 ? xint3) the devices support three masked external interrupts (xint1 ? xint3). each of the interrupts can be selected for negative, positive, or both negative and positive edge triggering and can also be enabled or disabled. these interrupts also contain a 16-bit free-running up counter, which is reset to zero when a valid interrupt edge is detected. this counter can be used to accurately time-stamp the interrupt. there are no dedicated pins for the external interrupts. xint1, xint2, and xint3 interrupts can accept inputs from gpio0 ? gpio31 pins. 6.1.14 internal zero pin oscillators, oscillator, and pll the device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a crystal attached to the on-chip oscillator circuit. a pll is provided supporting up to 16 input-clock-scaling ratios. the pll ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. refer to section 5 , specifications, for timing details. the pll block can be set in bypass mode. a second pll (pll2) feeds the hrcap module. 6.1.15 watchdog each device contains two watchdogs: cpu-watchdog that monitors the core and nmi-watchdog that is a missing clock-detect circuit. the user software must regularly reset the cpu-watchdog counter within a certain time frame; otherwise, the cpu-watchdog generates a reset to the processor. the cpu-watchdog can be disabled if necessary. the nmi-watchdog engages only in case of a clock failure and can either generate an interrupt or a device reset. 6.1.16 peripheral clocking the clocks to each individual peripheral can be enabled or disabled to reduce power consumption when a peripheral is not in use. additionally, the system clock to the serial ports (except i 2 c) can be scaled relative to the cpu clock. 6.1.17 low-power modes the devices are full static cmos devices. three low-power modes are provided: idle: places cpu in low-power mode. peripheral clocks may be turned off selectively and only those peripherals that need to function during idle are left operating. an enabled interrupt from an active peripheral or the watchdog timer will wake the processor from idle mode. standby: turns off clock to cpu and peripherals. this mode leaves the oscillator and pll functional. an external interrupt event will wake the processor and the peripherals. execution begins on the next valid cycle after detection of the interrupt event halt: this mode basically shuts down the device and places it in the lowest possible power- consumption mode. if the internal zero-pin oscillators are used as the clock source, the halt mode turns them off, by default. to keep these oscillators from shutting down, the intoscnhalti bits in clkctl register may be used. the zero-pin oscillators may thus be used to clock the cpu-watchdog in this mode. if the on-chip crystal oscillator is used as the clock source, it is shut down in this mode. a reset or an external signal (through a gpio pin) or the cpu-watchdog can wake the device from this mode. the cpu clock (oscclk) and wdclk should be from the same clock source before attempting to put the device into halt or standby.
44 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.1.18 peripheral frames 0, 1, 2, 3 (pfn) the device segregates peripherals into four sections. the mapping of peripherals is as follows: pf0: pie: pie interrupt enable and control registers plus pie vector table flash: flash waitstate registers timers: cpu-timers 0, 1, 2 registers csm: code security module key registers adc: adc result registers cla: control law accelrator registers and message rams pf1: gpio: gpio mux configuration and control registers ecan: enhanced control area network configuration and control registers pf2: sys: system control registers sci: serial communications interface (sci) control and rx/tx registers spi: serial port interface (spi) control and rx/tx registers adc: adc status, control, and configuration registers i 2 c: inter-integrated circuit module and registers xint: external interrupt registers pf3: mcbsp: multichannel buffered serial port registers epwm: enhanced pulse width modulator module and registers ecap: enhanced capture module and registers eqep: enhanced quadrature encoder pulse module and registers comparators: comparator modules usb: universal serial bus module and registers 6.1.19 general-purpose input/output (gpio) multiplexer most of the peripheral signals are multiplexed with general-purpose input/output (gpio) signals. this enables the user to use a pin as gpio if the peripheral signal or function is not used. on reset, gpio pins are configured as inputs. the user can individually program each pin for gpio mode or peripheral signal mode. for specific inputs, the user can also select the number of input qualification cycles. this is to filter unwanted noise glitches. the gpio signals can also be used to bring the device out of specific low-power modes.
45 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.1.20 32-bit cpu-timers (0, 1, 2) cpu-timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. the timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. the counter is decremented at the cpu clock speed divided by the prescale value setting. when the counter reaches zero, it is automatically reloaded with a 32-bit period value. cpu-timer 0 is for general use and is connected to the pie block. cpu-timer 1 is also for general use and can be connected to int13 of the cpu. cpu-timer 2 is reserved for sys/bios. cpu-timer 2 is connected to int14 of the cpu. if sys/bios is not being used, cpu-timer 2 is available for general use. cpu-timer 2 can be clocked by any one of the following: ? sysclkout (default) ? internal zero-pin oscillator 1 (intosc1) ? internal zero-pin oscillator 2 (intsoc2) ? external clock source 6.1.21 control peripherals the devices support the following peripherals that are used for embedded control and communication: epwm: the enhanced pwm peripheral supports independent/complementary pwm generation, adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. some of the pwm pins support the hrpwm high-resolution duty and period features. the type 1 module found on 2806x devices also supports increased dead-band resolution, enhanced soc and interrupt generation, and advanced triggering including trip functions based on comparator outputs. ecap: the enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in continuous/one-shot capture modes. this peripheral can also be configured to generate an auxiliary pwm signal. eqep: the enhanced qep peripheral uses a 32-bit position counter, supports low-speed measurement using capture unit and high-speed measurement using a 32-bit unit timer. this peripheral has a watchdog timer to detect motor stall and input error detection logic to identify simultaneous edge transition in qep signals. adc: the adc block is a 12-bit converter. the adc has up to 16 single-ended channels pinned out, depending on the device. the adc also contains two sample-and-hold units for simultaneous sampling. comparator: each comparator block consists of one analog comparator along with an internal 10-bit reference for supplying one input of the comparator. hrcap: the high-resolution capture peripheral operates in normal capture mode through a 16-bit counter clocked off of the hccapclk or in high-resolution capture mode by using built-in calibration logic in conjunction with a ti-supplied calibration library.
46 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.1.22 serial port peripherals the devices support the following serial communication peripherals: spi: the spi is a high-speed, synchronous serial i/o port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. normally, the spi is used for communications between the mcu and external peripherals or another processor. typical applications include external i/o or peripheral expansion through devices such as shift registers, display drivers, and adcs. multi-device communications are supported by the master/slave operation of the spi. the spi contains a 4-level receive and transmit fifo for reducing interrupt servicing overhead. sci: the serial communications interface is a 2-wire asynchronous serial port, commonly known as uart. the sci contains a 4-level receive and transmit fifo for reducing interrupt servicing overhead. i 2 c: the inter-integrated circuit (i 2 c) module provides an interface between a mcu and other devices compliant with philips semiconductors inter-ic bus ( i 2 c-bus ? ) specification version 2.1 and connected by way of an i 2 c-bus. external components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to or from the mcu through the i 2 c module. the i 2 c contains a 4-level receive- and-transmit fifo for reducing interrupt servicing overhead. ecan: this is the enhanced version of the can peripheral. the ecan supports 32 mailboxes, time stamping of messages, and is compliant with iso11898-1 (can 2.0b). mcbsp: the multichannel buffered serial port (mcbsp) connects to e1/t1 lines, phone- quality codecs for modem applications or high-quality stereo audio dac devices. the mcbsp receive and transmit registers are supported by the dma to significantly reduce the overhead for servicing this peripheral. each mcbsp module can be configured as an spi as required. usb: the usb peripheral, which conforms to the usb 2.0 specification, may be used as either a full-speed (12-mbps) device controller, or a full-speed (12-mbps) or low- speed (1.5-mbps) host controller. the controller supports a total of six user- configurable endpoints ? all of which can be accessed through dma, in addition to a dedicated control endpoint for endpoint zero. all packets transmitted or received are buffered in 4kb of dedicated endpoint memory. the usb peripheral supports all four transfer types: control, interrupt, bulk, and isochronous. because of the complexity of the usb peripheral and the associated protocol overhead, a full software library with application examples is provided within controlsuite ? .
47 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.2 memory maps in figure 6-1 through figure 6-8 , the following apply: ? memory blocks are not to scale. ? peripheral frame 0, peripheral frame 1, peripheral frame 2, and peripheral frame 3 memory maps are restricted to data memory only. a user program cannot access these memory maps in program space. ? protected means the order of write-followed-by-read operations is preserved rather than the pipeline order. ? certain memory ranges are eallow protected against spurious writes after configuration. ? locations 0x3d 7c80 ? 0x3d 7cc0 contain the internal oscillator and adc calibration routines. these locations are not programmable by the user. ? all devices with usb have the usb control registers mapped from 0x4000 to 0x4fff and 2k 16 ram from 0x40000 to 0x40800. when the clock to the usb module is enabled, this ram is connected to the usb controller and acts as the fifo ram. when the clock to the usb module is disabled, this ram is remapped to the cpu-accessible address space and can be used as general-purpose ram.
48 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated a. on non-usb devices, 0x00 4000 ? 0x00 4fff is reserved. b. on 2806xm and 2806xf devices only. figure 6-1. 28069 memory map m0 vector ram (enabled if vmap = 0) m0 saram (1k 16, 0-wait) 0x00 00000x00 0040 m1 saram (1k 16, 0-wait) 0x00 0400 data space prog space 0x00 2000 reserved peripheral frame 0 0x00 08000x00 1580 0x00 0d00 pie vector - ram (256 16) (enabled if vmap = 1, enpie = 1) 0x00 1400 0x00 0e00 0x00 1500 0x00 1480 cpu-to-cla message ram cla-to-cpu message ram cla registers peripheral frame 0 peripheral frame 3 (4k 16, protected) dma-accessible 0x00 5000 0x00 4000 peripheral frame 2 (4k 16, protected) 0x00 70000x00 8000 l0 dpsaram (2k 16) (0-wait, secure zone + ecsl, cla data ram2) 0x00 8800 l1 dpsaram (1k 16) (0-wait, secure zone + ecsl, cla data ram 0) 0x00 8c00 l2 dpsaram (1k 16) (0-wait, secure zone + ecsl, cla data ram 1) 0x00 9000 l3 dpsaram (4k 16) (0-wait, secure zone + ecsl, cla program ram) 0x00 a000 l4 saram (8k 16) (0-wait, secure zone + ecsl) 0x00 c000 l5 dpsaram (8k 16) (0-wait, dma ram 0) l8 dpsaram (8k 16) (0-wait, dma ram 3) l7 dpsaram (8k 16) (0-wait, dma ram 2) l6 dpsaram (8k 16) (0-wait, dma ram 1) 0x00 e000 0x01 00000x01 2000 peripheral frame 1 (4k 16, protected) usb control registers (a) 0x00 6000 0x3d 7800 user otp (1k 16, secure zone + ecsl) 0x3d 7c80 calibration data 0x01 4000 reserved 0x3d 7bfa reserved flash (128k 16, 8 sectors, secure zone + ecsl) fast and spintac libraries (16k 16, 0-wait) (b) 128-bit password 0x3d 8000 0x3f 7ff8 0x3f 8000 0x3f c000 boot rom (16k 16, 0-wait) vector (32 vectors, enabled if vmap = 1) 0x3f ffc0 0x3d 7cc0 get_mode function 0x3d 7cd0 0x3d 7e80 partid reserved 0x3d 7eb0 reserved reserved reserved reserved calibration data
49 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated a. on non-usb devices, 0x00 4000 ? 0x00 4fff is reserved. b. on 2806xm and 2806xf devices only. figure 6-2. 28068 memory map m0 vector ram (enabled if vmap = 0) m0 saram (1k 16, 0-wait) 0x00 00000x00 0040 m1 saram (1k 16, 0-wait) 0x00 0400 data space prog space reserved peripheral frame 0 0x00 0800 0x00 0d00 pie vector - ram (256 16) (enabled if vmap = 1, enpie = 1) 0x00 0e00 peripheral frame 0 0x00 1400 reserved 0x00 8000 l0 dpsaram (2k 16) (0-wait, secure zone + ecsl) 0x00 8800 l1 dpsaram (1k 16) (0-wait, secure zone + ecsl) 0x00 8c00 l2 dpsaram (1k 16) (0-wait, secure zone + ecsl) 0x00 9000 l3 dpsaram (4k 16) (0-wait, secure zone + ecsl) 0x00 a000 l4 saram (8k 16) (0-wait, secure zone + ecsl) 0x00 c000 l5 dpsaram (8k 16) (0-wait, dma ram 0) l8 dpsaram (8k 16) (0-wait, dma ram 3) l7 dpsaram (8k 16) (0-wait, dma ram 2) l6 dpsaram (8k 16) (0-wait, dma ram 1) 0x00 e000 0x01 0000 0x01 2000 reserved 0x01 4000 reserved 0x3d 7800 user otp (1k 16, secure zone + ecsl) 0x3d 7c80 calibration data 0x3d 7bfa reserved flash (128k 16, 8 sectors, secure zone + ecsl) fast and spintac libraries (16k 16, 0-wait) (b) 128-bit password 0x3d 8000 0x3f 7ff8 0x3f 8000 0x3f c000 boot rom (16k 16, 0-wait) vector (32 vectors, enabled if vmap = 1) 0x3f ffc0 0x3d 7cc0 get_mode function 0x3d 7cd0 reserved 0x3d 7e80 partid calibration data reserved 0x3d 7eb0 peripheral frame 3 (4k 16, protected) dma-accessible 0x00 5000 0x00 4000 peripheral frame 2 (4k 16, protected) 0x00 7000 peripheral frame 1 (4k 16, protected) usb control registers (a) 0x00 6000
50 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated a. on non-usb devices, 0x00 4000 ? 0x00 4fff is reserved. figure 6-3. 28067 memory map m0 vector ram (enabled if vmap = 0) m0 saram (1k 16, 0-wait) 0x00 00000x00 0040 m1 saram (1k 16, 0-wait) 0x00 0400 data space prog space reserved peripheral frame 0 0x00 0800 0x00 0d00 pie vector - ram (256 16) (enabled if vmap = 1, enpie = 1) 0x00 0e00 peripheral frame 0 0x00 1400 reserved 0x00 8000 l0 dpsaram (2k 16) (0-wait, secure zone + ecsl) 0x00 8800 l1 dpsaram (1k 16) (0-wait, secure zone + ecsl) 0x00 8c00 l2 dpsaram (1k 16) (0-wait, secure zone + ecsl) 0x00 9000 l3 dpsaram (4k 16) (0-wait, secure zone + ecsl) 0x00 a000 l4 saram (8k 16) (0-wait, secure zone + ecsl) 0x00 c000 l5 dpsaram (8k 16) (0-wait, dma ram 0) l8 dpsaram (8k 16) (0-wait, dma ram 3) l7 dpsaram (8k 16) (0-wait, dma ram 2) l6 dpsaram (8k 16) (0-wait, dma ram 1) 0x00 e000 0x01 0000 0x01 2000 reserved 0x01 4000 reserved 0x3d 7800 user otp (1k 16, secure zone + ecsl) 0x3d 7c80 calibration data 0x3d 7bfa reserved flash (128k 16, 8 sectors, secure zone + ecsl) 128-bit password 0x3d 8000 0x3f 7ff8 boot rom (32k 16, 0-wait) vector (32 vectors, enabled if vmap = 1) 0x3f 8000 0x3f ffc0 0x3d 7cc0 get_mode function 0x3d 7cd0 reserved 0x3d 7e80 partid calibration data reserved 0x3d 7eb0 peripheral frame 3 (4k 16, protected) dma-accessible 0x00 5000 0x00 4000 peripheral frame 2 (4k 16, protected) 0x00 7000 peripheral frame 1 (4k 16, protected) usb control registers (a) 0x00 6000
51 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated a. on non-usb devices, 0x00 4000 ? 0x00 4fff is reserved. figure 6-4. 28066 memory map m0 vector ram (enabled if vmap = 0) m0 saram (1k 16, 0-wait) 0x00 00000x00 0040 m1 saram (1k 16, 0-wait) 0x00 0400 data space prog space reserved peripheral frame 0 0x00 0800 0x00 0d00 pie vector - ram (256 16) (enabled if vmap = 1, enpie = 1) 0x00 0e00 peripheral frame 0 0x00 1400 reserved 0x00 8000 l0 dpsaram (2k 16) (0-wait, secure zone + ecsl) 0x00 8800 l1 dpsaram (1k 16) (0-wait, secure zone + ecsl) 0x00 8c00 l2 dpsaram (1k 16) (0-wait, secure zone + ecsl) 0x00 9000 l3 dpsaram (4k 16) (0-wait, secure zone + ecsl) 0x00 a000 l4 saram (8k 16) (0-wait, secure zone + ecsl) 0x00 c000 l5 dpsaram (8k 16) (0-wait, dma ram 0) l6 dpsaram (8k 16) (0-wait, dma ram 1) 0x00 e000 reserved 0x01 0000 reserved 0x3d 7800 user otp (1k 16, secure zone + ecsl) 0x3d 7c80 calibration data 0x3d 7bfa reserved flash (128k 16, 8 sectors, secure zone + ecsl) 128-bit password 0x3d 8000 0x3f 7ff8 boot rom (32k 16, 0-wait) vector (32 vectors, enabled if vmap = 1) 0x3f 8000 0x3f ffc0 0x3d 7cc0 get_mode function 0x3d 7cd0 reserved 0x3d 7e80 partid calibration data reserved 0x3d 7eb0 peripheral frame 3 (4k 16, protected) dma-accessible 0x00 5000 0x00 4000 peripheral frame 2 (4k 16, protected) 0x00 7000 peripheral frame 1 (4k 16, protected) usb control registers (a) 0x00 6000
52 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated a. on non-usb devices, 0x00 4000 ? 0x00 4fff is reserved. figure 6-5. 28065 memory map m0 vector ram (enabled if vmap = 0) m0 saram (1k 16, 0-wait) 0x00 00000x00 0040 m1 saram (1k 16, 0-wait) 0x00 0400 data space prog space reserved 0x00 2000 reserved peripheral frame 0 0x00 08000x00 1580 0x00 0d00 pie vector - ram (256 16) (enabled if vmap = 1, enpie = 1) 0x00 1400 0x00 0e00 0x00 1500 0x00 1480 cpu-to-cla message ram cla-to-cpu message ram cla registers peripheral frame 0 0x00 8000 l0 dpsaram (2k 16) (0-wait, secure zone + ecsl, cla data ram2) 0x00 8800 l1 dpsaram (1k 16) (0-wait, secure zone + ecsl, cla data ram 0) 0x00 8c00 l2 dpsaram (1k 16) (0-wait, secure zone + ecsl, cla data ram 1) 0x00 9000 l3 dpsaram (4k 16) (0-wait, secure zone + ecsl, cla program ram) 0x00 a000 l4 saram (8k 16) (0-wait, secure zone + ecsl) 0x00 c000 l5 dpsaram (8k 16) (0-wait, dma ram 0) l8 dpsaram (8k 16) (0-wait, dma ram 3) l7 dpsaram (8k 16) (0-wait, dma ram 2) l6 dpsaram (8k 16) (0-wait, dma ram 1) 0x00 e000 0x01 0000 0x01 2000 reserved 0x01 4000 reserved reserved 0x3d 7800 user otp (1k 16, secure zone + ecsl) 0x3d 7c80 calibration data 0x3d 7bfa reserved flash (64k 16, 8 sectors, secure zone + ecsl) 128-bit password 0x3e 8000 0x3f 7ff8 boot rom (32k 16, 0-wait) vector (32 vectors, enabled if vmap = 1) 0x3f 8000 0x3f ffc0 0x3d 7cc0 get_mode function 0x3d 7cd0 reserved 0x3d 7e80 partid calibration data reserved 0x3d 7eb0 peripheral frame 3 (4k 16, protected) dma-accessible 0x00 5000 0x00 4000 peripheral frame 2 (4k 16, protected) 0x00 7000 peripheral frame 1 (4k 16, protected) usb control registers (a) 0x00 6000
53 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated a. on non-usb devices, 0x00 4000 ? 0x00 4fff is reserved. figure 6-6. 28064 memory map m0 vector ram (enabled if vmap = 0) m0 saram (1k 16, 0-wait) 0x00 00000x00 0040 m1 saram (1k 16, 0-wait) 0x00 0400 data space prog space reserved peripheral frame 0 0x00 0800 0x00 0d00 pie vector - ram (256 16) (enabled if vmap = 1, enpie = 1) 0x00 0e00 peripheral frame 0 0x00 1400 reserved l0 dpsaram (2k 16) (0-wait, secure zone + ecsl) 0x00 8800 l1 dpsaram (1k 16) (0-wait, secure zone + ecsl) 0x00 8c00 l2 dpsaram (1k 16) (0-wait, secure zone + ecsl) 0x00 9000 l3 dpsaram (4k 16) (0-wait, secure zone + ecsl) 0x00 a000 l4 saram (8k 16) (0-wait, secure zone + ecsl) 0x00 c000 l5 dpsaram (8k 16) (0-wait, dma ram 0) l8 dpsaram (8k 16) (0-wait, dma ram 3) l7 dpsaram (8k 16) (0-wait, dma ram 2) l6 dpsaram (8k 16) (0-wait, dma ram 1) 0x00 e000 0x01 0000 0x01 2000 reserved 0x01 4000 reserved 0x3d 7800 user otp (1k 16, secure zone + ecsl) 0x3d 7c80 calibration data 0x3d 7bfa reserved flash (64k 16, 8 sectors, secure zone + ecsl) 128-bit password 0x3e 8000 0x3f 7ff8 boot rom (32k 16, 0-wait) vector (32 vectors, enabled if vmap = 1) 0x3f 8000 0x3f ffc0 0x3d 7cc0 get_mode function 0x3d 7cd0 reserved 0x3d 7e80 partid calibration data reserved 0x3d 7eb0 peripheral frame 3 (4k 16, protected) dma-accessible 0x00 5000 0x00 4000 peripheral frame 2 (4k 16, protected) 0x00 7000 peripheral frame 1 (4k 16, protected) usb control registers (a) 0x00 6000
54 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated a. on non-usb devices, 0x00 4000 ? 0x00 4fff is reserved. figure 6-7. 28063 memory map m0 vector ram (enabled if vmap = 0) m0 saram (1k 16, 0-wait) 0x00 00000x00 0040 m1 saram (1k 16, 0-wait) 0x00 0400 data space prog space reserved peripheral frame 0 0x00 0800 0x00 0d00 pie vector - ram (256 16) (enabled if vmap = 1, enpie = 1) 0x00 0e00 peripheral frame 0 0x00 1400 reserved 0x00 8000 l0 dpsaram (2k 16) (0-wait, secure zone + ecsl) 0x00 8800 l1 dpsaram (1k 16) (0-wait, secure zone + ecsl) 0x00 8c00 l2 dpsaram (1k 16) (0-wait, secure zone + ecsl) 0x00 9000 l3 dpsaram (4k 16) (0-wait, secure zone + ecsl) 0x00 a000 l4 saram (8k 16) (0-wait, secure zone + ecsl) 0x00 c000 l5 dpsaram (8k 16) (0-wait, dma ram 0) l6 dpsaram (8k 16) (0-wait, dma ram 1) 0x00 e000 reserved 0x01 0000 reserved 0x3d 7800 user otp (1k 16, secure zone + ecsl) 0x3d 7c80 calibration data 0x3d 7bfa reserved flash (64k 16, 8 sectors, secure zone + ecsl) 128-bit password 0x3e 8000 0x3f 7ff8 boot rom (32k 16, 0-wait) vector (32 vectors, enabled if vmap = 1) 0x3f 8000 0x3f ffc0 0x3d 7cc0 get_mode function 0x3d 7cd0 reserved 0x3d 7e80 partid calibration data reserved 0x3d 7eb0 peripheral frame 3 (4k 16, protected) dma-accessible 0x00 5000 0x00 4000 peripheral frame 2 (4k 16, protected) 0x00 7000 peripheral frame 1 (4k 16, protected) usb control registers (a) 0x00 6000
55 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated a. on non-usb devices, 0x00 4000 ? 0x00 4fff is reserved. b. on 2806xm and 2806xf devices only. figure 6-8. 28062 memory map m0 vector ram (enabled if vmap = 0) m0 saram (1k 16, 0-wait) 0x00 00000x00 0040 m1 saram (1k 16, 0-wait) 0x00 0400 data space prog space reserved peripheral frame 0 0x00 0800 0x00 0d00 pie vector - ram (256 16) (enabled if vmap = 1, enpie = 1) 0x00 0e00 peripheral frame 0 0x00 1400 reserved 0x00 8000 l0 dpsaram (2k 16) (0-wait, secure zone + ecsl) 0x00 8800 l1 dpsaram (1k 16) (0-wait, secure zone + ecsl) 0x00 8c00 l2 dpsaram (1k 16) (0-wait, secure zone + ecsl) 0x00 9000 l3 dpsaram (4k 16) (0-wait, secure zone + ecsl) 0x00 a000 l4 saram (8k 16) (0-wait, secure zone + ecsl) 0x00 c000 l5 dpsaram (8k 16) (0-wait, dma ram 0) reserved 0x00 e000 reserved 0x3d 7800 user otp (1k 16, secure zone + ecsl) 0x3d 7c80 calibration data 0x3d 7bfa reserved flash (64k 16, 8 sectors, secure zone + ecsl) fast and spintac libraries (16k 16, 0-wait) (b) 128-bit password 0x3e 8000 0x3f 7ff8 0x3f 8000 0x3f c000 boot rom (16k 16, 0-wait) vector (32 vectors, enabled if vmap = 1) 0x3f ffc0 0x3d 7cc0 get_mode function 0x3d 7cd0 reserved 0x3d 7e80 partid calibration data reserved 0x3d 7eb0 peripheral frame 3 (4k 16, protected) dma-accessible 0x00 5000 0x00 4000 peripheral frame 2 (4k 16, protected) 0x00 7000 peripheral frame 1 (4k 16, protected) usb control registers (a) 0x00 6000
56 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated table 6-3. addresses of flash sectors in f28069, f28068, f28067, f28066 address range program and data space 0x3d 8000 ? 0x3d bfff sector h (16k 16) 0x3d c000 ? 0x3d ffff sector g (16k 16) 0x3e 0000 ? 0x3e 3fff sector f (16k 16) 0x3e 4000 ? 0x3e 7fff sector e (16k 16) 0x3e 8000 ? 0x3e bfff sector d (16k 16) 0x3e c000 ? 0x3e ffff sector c (16k 16) 0x3f 0000 ? 0x3f 3fff sector b (16k 16) 0x3f 4000 ? 0x3f 7ff5 sector a (16k 16) 0x3f 7ff6 ? 0x3f 7ff7 boot-to-flash entry point (program branch instruction here) 0x3f 7ff8 ? 0x3f 7fff security password (128-bit) (do not program to all zeros) table 6-4. addresses of flash sectors in f28065, f28064, f28063, f28062 address range program and data space 0x3e 8000 ? 0x3e 9fff sector h (8k 16) 0x3e a000 ? 0x3e bfff sector g (8k 16) 0x3e c000 ? 0x3e dfff sector f (8k 16) 0x3e e000 ? 0x3e ffff sector e (8k 16) 0x3f 0000 ? 0x3f 1fff sector d (8k 16) 0x3f 2000 ? 0x3f 3fff sector c (8k 16) 0x3f 4000 ? 0x3f 5fff sector b (8k 16) 0x3f 6000 ? 0x3f 7ff5 sector a (8k 16) 0x3f 7ff6 ? 0x3f 7ff7 boot-to-flash entry point (program branch instruction here) 0x3f 7ff8 ? 0x3f 7fff security password (128-bit) (do not program to all zeros) note addresses 0x3f 7ff0 ? 0x3f 7ff5 are reserved for data and should not contain program code.
57 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated peripheral frame 1 and peripheral frame 2 are grouped together to enable these blocks to be write/read peripheral block protected. the protected mode makes sure that all accesses to these blocks happen as written. because of the pipeline, a write immediately followed by a read to different memory locations, will appear in reverse order on the memory bus of the cpu. this can cause problems in certain peripheral applications where the user expected the write to occur first (as written). the cpu supports a block protection mode where a region of memory can be protected so that operations occur as written (the penalty is extra cycles are added to align the operations). this mode is programmable and by default, it protects the selected zones. the wait-states for the various spaces in the memory map area are listed in table 6-5 . table 6-5. wait-states area wait-states (cpu) comments m0 and m1 sarams 0-wait fixed peripheral frame 0 0-wait peripheral frame 1 0-wait (writes) cycles can be extended by peripheral-generated ready. 2-wait (reads) back-to-back write operations to peripheral frame 1 registers will incur a 1-cycle stall (1-cycle delay). peripheral frame 2 0-wait (writes) fixed. cycles cannot be extended by the peripheral. 2-wait (reads) peripheral frame 3 0-wait (writes) assumes no conflict between cpu and cla/dma cycles. the wait states can be extended by peripheral-generated ready. 2-wait (reads) l0 ? l8 saram 0-wait data and program assumes no cpu conflicts otp programmable programmed through the flash registers. 1-wait minimum 1-wait is minimum number of wait states allowed. flash programmable programmed through the flash registers. 0-wait paged min 1-wait random min random paged flash password 16-wait fixed wait states of password locations are fixed. boot-rom 0-wait
58 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) registers in frame 0 support 16-bit and 32-bit accesses. (2) if registers are eallow protected, then writes cannot be performed until the eallow instruction is executed. the edis instruction disables writes to prevent stray code or pointers from corrupting register contents. (3) the flash registers are also protected by the code security module (csm). 6.3 register maps the devices contain four peripheral register spaces. the spaces are categorized as follows: peripheral frame 0: these are peripherals that are mapped directly to the cpu memory bus. see table 6-6 . peripheral frame 1: these are peripherals that are mapped to the 32-bit peripheral bus. see table 6-7 . peripheral frame 2: these are peripherals that are mapped to the 16-bit peripheral bus. see table 6-8 . peripheral frame 3: mcbsp registers are mapped to this. see table 6-9 . table 6-6. peripheral frame 0 registers (1) name address range size ( 16) eallow protected (2) device emulation registers 0x00 0880 ? 0x00 0984 261 yes system power control registers 0x00 0985 ? 0x00 0987 3 yes flash registers (3) 0x00 0a80 ? 0x00 0adf 96 yes code security module registers 0x00 0ae0 ? 0x00 0aef 16 yes adc registers (0 wait read only) 0x00 0b00 ? 0x00 0b0f 16 no cpu-timer0, cpu-timer1, cpu-timer2 registers 0x00 0c00 ? 0x00 0c3f 64 no pie registers 0x00 0ce0 ? 0x00 0cff 32 no pie vector table 0x00 0d00 ? 0x00 0dff 256 yes dma registers 0x00 1000 ? 0x00 11ff 512 yes cla registers 0x00 1400 ? 0x00 147f 128 yes cla to cpu message ram (cpu writes ignored) 0x00 1480 ? 0x00 14ff 128 na cpu to cla message ram (cla writes ignored) 0x00 1500 ? 0x00 157f 128 na
59 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) some registers are eallow protected. see the module reference guide for more information. table 6-7. peripheral frame 1 registers name address range size ( 16) eallow protected ecan-a registers 0x00 6000 ? 0x00 61ff 512 (1) hrcap1 registers 0x00 6ac0 ? 0x00 6adf 32 (1) hrcap2 registers 0x00 6ae0 ? 0x00 6aff 32 (1) hrcap3 registers 0x00 6c80 ? 0x00 6c9f 32 (1) hrcap4 registers 0x00 6ca0 ? 0x00 6cbf 32 (1) gpio registers 0x00 6f80 ? 0x00 6fff 128 (1) (1) some registers are eallow protected. see the module reference guide for more information. table 6-8. peripheral frame 2 registers name address range size ( 16) eallow protected system control registers 0x00 7010 ? 0x00 702f 32 yes spi-a registers 0x00 7040 ? 0x00 704f 16 no sci-a registers 0x00 7050 ? 0x00 705f 16 no nmi watchdog interrupt registers 0x00 7060 ? 0x00 706f 16 yes external interrupt registers 0x00 7070 ? 0x00 707f 16 yes adc registers 0x00 7100 ? 0x00 717f 128 (1) spi-b registers 0x00 7740 ? 0x00 774f 16 no sci-b registers 0x00 7750 ? 0x00 775f 16 no i2c-a registers 0x00 7900 ? 0x00 793f 64 (1) (1) some registers are eallow protected. see the module reference guide for more information. table 6-9. peripheral frame 3 registers name address range size ( 16) eallow protected usb0 registers 0x00 4000 ? 0x00 4fff 4096 no mcbsp-a registers 0x00 5000 ? 0x00 503f 64 no comparator 1 registers 0x00 6400 ? 0x00 641f 32 (1) comparator 2 registers 0x00 6420 ? 0x00 643f 32 (1) comparator 3 registers 0x00 6440 ? 0x00 645f 32 (1) epwm1 + hrpwm1 registers 0x00 6800 ? 0x00 683f 64 (1) epwm2 + hrpwm2 registers 0x00 6840 ? 0x00 687f 64 (1) epwm3 + hrpwm3 registers 0x00 6880 ? 0x00 68bf 64 (1) epwm4 + hrpwm4 registers 0x00 68c0 ? 0x00 68ff 64 (1) epwm5 + hrpwm5 registers 0x00 6900 ? 0x00 693f 64 (1) epwm6 + hrpwm6 registers 0x00 6940 ? 0x00 697f 64 (1) epwm7 + hrpwm7 registers 0x00 6980 ? 0x00 69bf 64 (1) epwm8 + hrpwm8 registers 0x00 69c0 ? 0x00 69ff 64 (1) ecap1 registers 0x00 6a00 ? 0x00 6a1f 32 no ecap2 registers 0x00 6a20 ? 0x00 6a3f 32 no ecap3 registers 0x00 6a40 ? 0x00 6a57 32 no eqep1 registers 0x00 6b00 ? 0x00 6b3f 64 (1) eqep2 registers 0x00 6b40 ? 0x00 6b7f 64 (1)
60 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.4 device emulation registers these registers are used to control the protection mode of the c28x cpu and to monitor some critical device signals. the registers are defined in table 6-10 . table 6-10. device emulation registers name address range size ( 16) description eallow protected devicecnf 0x0880 ? 0x0881 2 device configuration register yes partid 0x3d 7e80 1 part id register tms320f28069pzp/pz 0x009e no tms320f28069 u pzp/pz 0x009f tms320f28069 m pzp/pz 0x009e tms320f28069 f pzp/pz 0x009e tms320f28069pfp/pn 0x009c tms320f28069 u pfp/pn 0x009d tms320f28069 m pfp/pn 0x009c tms320f28069 f pfp/pn 0x009c tms320f28068pzp/pz 0x008e tms320f28068 u pzp/pz 0x008f tms320f28068 m pzp/pz 0x008e tms320f28068 f pzp/pz 0x008e tms320f28068pfp/pn 0x008c tms320f28068 u pfp/pn 0x008d tms320f28068 m pfp/pn 0x008c tms320f28068 f pfp/pn 0x008c tms320f28067pzp/pz 0x008a tms320f28067 u pzp/pz 0x008b tms320f28067pfp/pn 0x0088 tms320f28067 u pfp/pn 0x0089 tms320f28066pzp/pz 0x0086 tms320f28066 u pzp/pz 0x0087 tms320f28066pfp/pn 0x0084 tms320f28066 u pfp/pn 0x0085 tms320f28065pzp/pz 0x007e tms320f28065 u pzp/pz 0x007f tms320f28065pfp/pn 0x007c tms320f28065 u pfp/pn 0x007d tms320f28064pzp/pz 0x006e tms320f28064 u pzp/pz 0x006f tms320f28064pfp/pn 0x006c tms320f28064 u pfp/pn 0x006d tms320f28063pzp/pz 0x006a tms320f28063 u pzp/pz 0x006b tms320f28063pfp/pn 0x0068 tms320f28063 u pfp/pn 0x0069 tms320f28062pzp/pz 0x0066 tms320f28062 u pzp/pz 0x0067 tms320f28062 f pzp/pz 0x0066 tms320f28062pfp/pn 0x0064 tms320f28062 u pfp/pn 0x0065 tms320f28062 f pfp/pn 0x0064
61 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated table 6-10. device emulation registers (continued) name address range size ( 16) description eallow protected classid 0x0882 1 class id register tms320f28069 0x009f no tms320f28069 u 0x009f tms320f28069 m 0x009f tms320f28069 f 0x009f tms320f28068 0x008f tms320f28068 u 0x008f tms320f28068 m 0x008f tms320f28068 f 0x008f tms320f28067 0x008f tms320f28067 u 0x008f tms320f28066 0x008f tms320f28066 u 0x008f tms320f28065 0x007f tms320f28065 u 0x007f tms320f28064 0x006f tms320f28064 u 0x006f tms320f28063 0x006f tms320f28063 u 0x006f tms320f28062 0x006f tms320f28062 u 0x006f tms320f28062 f 0x006f revid 0x0883 1 revision id register 0x0000 - silicon rev. 0 - tmx no 0x0001 - silicon rev. a - tms 0x0002 - silicon rev. b - tms
62 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.5 vreg, bor, por although the core and i/o circuitry operate on two different voltages, these devices have an on-chip vreg to generate the v dd voltage from the v ddio supply. this eliminates the cost and space of a second external regulator on an application board. additionally, internal power-on reset (por) and brown-out reset (bor) circuits monitor both the v dd and v ddio rails during power-up and run mode. 6.5.1 on-chip vreg a linear regulator generates the core voltage (v dd ) from the v ddio supply. therefore, although capacitors are required on each v dd pin to stabilize the generated voltage, power need not be supplied to these pins to operate the device. conversely, the vreg can be disabled, should power or redundancy be the primary concern of the application. 6.5.1.1 using the on-chip vreg to use the on-chip vreg, the vregenz pin should be tied low and the appropriate recommended operating voltage should be supplied to the v ddio and v dda pins. in this case, the v dd voltage needed by the core logic will be generated by the vreg. each v dd pin requires on the order of 1.2 f (minimum) capacitance for proper regulation of the vreg. these capacitors should be located as close as possible to the v dd pins. 6.5.1.2 disabling the on-chip vreg to conserve power, it is also possible to disable the on-chip vreg and supply the core logic voltage to the v dd pins with a more efficient external regulator. to enable this option, the vregenz pin must be tied high. 6.5.2 on-chip power-on reset (por) and brown-out reset (bor) circuit two on-chip supervisory circuits, the power-on reset (por) and the brown-out reset (bor) remove the burden of monitoring the v dd and v ddio supply rails from the application board. the purpose of the por is to create a clean reset throughout the device during the entire power-up procedure. the trip point is a looser, lower trip point than the bor, which watches for dips in the v dd or v ddio rail during device operation. the por function is present on both v dd and v ddio rails at all times. after initial device power- up, the bor function is present on v ddio at all times, and on v dd when the internal vreg is enabled ( vregenz pin is tied low). both functions tie the xrs pin low when one of the voltages is below their respective trip point. additionally, when the internal voltage regulator is enabled, an over-voltage protection circuit will tie xrs low if the v dd rail rises above its trip point. see section 5 for the various trip points as well as the delay time for the device to release the xrs pin after the under-voltage or over- voltage condition is removed. figure 6-9 shows the vreg, por, and bor. to disable both the v dd and v ddio bor functions, a bit is provided in the borcfg register. see the systems control and interrupts chapter of the tms320x2806x piccolo technical reference manual ( spruh18 ) for details.
63 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated a. wdrst is the reset signal from the cpu-watchdog. b. pbrs is the reset signal from the por/bor module. figure 6-9. vreg + por + bor + reset signal connectivity i/o pin in out dir (0 = input, 1 = output) (force hi-z when high) sysrs c28 core sync rs pll + clocking logic mclkrs vreghalt deglitch filter on-chip voltage regulator (vreg) vregenz por/bor generating module xrs pin wdrst sysclkout wdrst (a) jtag tck detect logic pbrs (b) internal weak pu
64 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) all registers in this table are eallow protected. 6.6 system control this section describes the oscillator and clocking mechanisms, the watchdog function and the low power modes. table 6-11. pll, clocking, watchdog, and low-power mode registers name address size ( 16) description (1) borcfg 0x00 0985 1 bor configuration register xclk 0x00 7010 1 xclkout control pllsts 0x00 7011 1 pll status register clkctl 0x00 7012 1 clock control register plllockprd 0x00 7013 1 pll lock period intosc1trim 0x00 7014 1 internal oscillator 1 trim register intosc2trim 0x00 7016 1 internal oscillator 2 trim register pclkcr2 0x00 7019 1 peripheral clock control register 2 lospcp 0x00 701b 1 low-speed peripheral clock prescaler register pclkcr0 0x00 701c 1 peripheral clock control register 0 pclkcr1 0x00 701d 1 peripheral clock control register 1 lpmcr0 0x00 701e 1 low power mode control register 0 pclkcr3 0x00 7020 1 peripheral clock control register 3 pllcr 0x00 7021 1 pll control register scsr 0x00 7022 1 system control and status register wdcntr 0x00 7023 1 watchdog counter register wdkey 0x00 7025 1 watchdog reset key register wdcr 0x00 7029 1 watchdog control register jtagdebug 0x00 702a 1 jtag port debug register pll2ctl 0x00 7030 1 pll2 configuration register pll2mult 0x00 7032 1 pll2 multiplier register pll2sts 0x00 7034 1 pll2 lock status register sysclk2cntr 0x00 7036 1 sysclk2 clock counter register epwmcfg 0x00 703a 1 epwm dma/cla configuration register
65 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated figure 6-10 shows the various clock domains that are discussed. figure 6-11 shows the various clock sources (both internal and external) that can provide a clock for device operation. a. clkin is the clock into the cpu. clkin is passed out of the cpu as sysclkout (that is, clkin is the same frequency as sysclkout). figure 6-10. clock and reset domains lospcp (system ctrl regs) peripheral registers spi-a, spi-b, sci-a, sci-b pf2 lspclk sysclkout c28x core clkin peripheral registers usb pf3 gpio mux lospcp (system ctrl regs) peripheral registers mcbsp pf3 lspclk peripheral registers ecan-a pf1 peripheral registers ecap1, ecap2, ecap3 eqep1, eqep2 pf3 peripheral registers epwm1, epwm2, epwm3, epwm4, epwm5, epwm6, epwm7, epwm8 pf3 peripheral registers i2c-a pf2 peripheral registers hrcap1, hrcap2, hrcap3, hrcap4 pf1 adc registers 12-bit adc 16 ch pf2 pf0 comp registers comp1, comp2, comp3 pf3 6 analog gpio mux /2 pclkcr0/1/2/3 (system ctrl regs) clock enables clock enablesclock enables clock enables clock enables clock enables clock enables clock enables clock enables clock enables pll2 i/o i/o i/o i/o i/o i/o i/o i/o
66 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated a. register loaded from ti otp-based calibration function. b. see section 6.6.5 for details on missing clock detection. figure 6-11. clock tree intosc1trim reg (a) internal osc 1 (10 mhz) osce clkctl[intosc1off] wakeosc clkctl[intosc1halt] intosc2trim reg (a) internal osc 2 (10 mhz) osce clkctl[intosc2off] clkctl[intosc2halt] 1 = turn osc off 1 = ignore halt 1 = turn osc off 1 = ignore halt xclk[xclkinsel] 0 = gpio381 = gpio19 gpio19 or gpio38 clkctl[xclkinoff] 0 0 1 (crystal) osc xclkin x1 x2 clkctl[xtaloscoff] 0 = osc on (default on reset) 1 = turn osc off 0 1 0 1 osc1clk oscclksrc1 wdclk osc2clk 0 1 clkctl[wdclksrcsel] (osc1clk on reset) xrs clkctl[oscclksrcsel] clkctl[trm2clkprescale] clkctl[tmr2clksrcsel] oscclksrc2 11 prescale /1, /2, /4, /8, /16 00 01, 10, 11 cputmr2clk sync edge detect 10 01 clkctl[oscclksrc2sel] sysclkout wakeosc (oscillators enabled when this signal is high) extclk xtal xclkin (osc1clk on reset) xrs oscclk pll missing-clock-detect circuit (b) cpu-watchdog pll2ctl.pll2clksrcsel pll2ctl.pll2en sysclk2 to usb and hrcap blocks pll2 /2
67 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.6.1 internal zero pin oscillators the f2806x devices contain two independent internal zero pin oscillators. by default both oscillators are turned on at power up, and internal oscillator 1 is the default clock source at this time. for power savings, unused oscillators may be powered down by the user. the center frequency of these oscillators is determined by their respective oscillator trim registers, written to in the calibration routine as part of the boot rom execution. see section 6.9 for more information on these oscillators. 6.6.2 crystal oscillator option the on-chip crystal oscillator x1 and x2 pins are 1.8-v level signals and must never have 3.3-v level signals applied to them. if a system 3.3-v external oscillator is to be used as a clock source, it should be connected to the xclkin pin only. the x1 pin is not intended to be used as a single-ended clock input, it should be used with x2 and a crystal. the typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in table 6-12 . furthermore, esr range = 30 to 150 ? . (1) c shunt should be less than or equal to 5 pf. table 6-12. typical specifications for external quartz crystal (1) frequency (mhz) r d ( ? ) c l1 (pf) c l2 (pf) 5 2200 18 18 10 470 15 15 15 0 15 15 20 0 12 12 figure 6-12. using the on-chip crystal oscillator note 1. c l1 and c l2 are the total capacitance of the circuit board and components excluding the ic and crystal. the value is usually approximately twice the value of the load capacitance of the crystal. 2. the load capacitance of the crystal is described in the crystal specifications of the manufacturers. 3. ti recommends that customers have the resonator/crystal vendor characterize the operation of their device with the mcu chip. the resonator/crystal vendor has the equipment and expertise to tune the tank circuit. the vendor can also advise the customer regarding the proper tank component values that will produce proper start up and stability over the entire operating range. x2 x1 crystal xclkin/gpio19/38 turn off xclkin path in clkctl register r d c l1 c l2
68 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) the pll control register (pllcr) and pll status register (pllsts) are reset to their default state by the xrs signal or a watchdog reset only. a reset issued by the debugger or the missing clock detect logic has no effect. (2) this register is eallow protected. see the systems control and interrupts chapter of the tms320x2806x piccolo technical reference manual ( spruh18 ) for more information. (3) by default, pllsts[divsel] is configured for /4. (the boot rom changes this to /1.) pllsts[divsel] must be 0 before writing to the pllcr and should be changed only after pllsts[plllocks] = 1. figure 6-13. using a 3.3-v external oscillator 6.6.3 pll-based clock module the devices have an on-chip, pll-based clock module. this module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. the pll has a 5-bit ratio control pllcr[div] to select different cpu clock rates. the watchdog module should be disabled before writing to the pllcr register. the watchdog module can be re-enabled (if need be) after the pll module has stabilized, which takes 1 ms. the input clock and pllcr[div] bits should be chosen in such a way that the output frequency of the pll (vcoclk) is at least 50 mhz. table 6-13. pll settings pllcr[div] value (1) (2) sysclkout (clkin) pllsts[divsel] = 0 or 1 (3) pllsts[divsel] = 2 pllsts[divsel] = 3 00000 (pll bypass) oscclk/4 (default) (1) oscclk/2 oscclk 00001 (oscclk * 1)/4 (oscclk * 1)/2 (oscclk * 1)/1 00010 (oscclk * 2)/4 (oscclk * 2)/2 (oscclk * 2)/1 00011 (oscclk * 3)/4 (oscclk * 3)/2 (oscclk * 3)/1 00100 (oscclk * 4)/4 (oscclk * 4)/2 (oscclk * 4)/1 00101 (oscclk * 5)/4 (oscclk * 5)/2 (oscclk * 5)/1 00110 (oscclk * 6)/4 (oscclk * 6)/2 (oscclk * 6)/1 00111 (oscclk * 7)/4 (oscclk * 7)/2 (oscclk * 7)/1 01000 (oscclk * 8)/4 (oscclk * 8)/2 (oscclk * 8)/1 01001 (oscclk * 9)/4 (oscclk * 9)/2 (oscclk * 9)/1 01010 (oscclk * 10)/4 (oscclk * 10)/2 (oscclk * 10)/1 01011 (oscclk * 11)/4 (oscclk * 11)/2 (oscclk * 11)/1 01100 (oscclk * 12)/4 (oscclk * 12)/2 (oscclk * 12)/1 01101 (oscclk * 13)/4 (oscclk * 13)/2 (oscclk * 13)/1 01110 (oscclk * 14)/4 (oscclk * 14)/2 (oscclk * 14)/1 01111 (oscclk * 15)/4 (oscclk * 15)/2 (oscclk * 15)/1 10000 (oscclk * 16)/4 (oscclk * 16)/2 (oscclk * 16)/1 10001 (oscclk * 17)/4 (oscclk * 17)/2 (oscclk * 17)/1 10010 (oscclk * 18)/4 (oscclk * 18)/2 (oscclk * 18)/1 table 6-14. clkin divide options pllsts [divsel] clkin divide 0 /4 1 /4 2 /2 3 /1 external clock signal (toggling 0?v ddio ) xclkin/gpio19/38 x2 nc x1
69 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated the pll-based clock module provides four modes of operation: ? i ntosc1 (internal zero-pin oscillator 1): this is the on-chip internal oscillator 1. this can provide the clock for the watchdog block, core and cpu-timer 2 ? intosc2 (internal zero-pin oscillator 2): this is the on-chip internal oscillator 2. this can provide the clock for the watchdog block, core and cpu-timer 2. both intosc1 and intosc2 can be independently chosen for the watchdog block, core and cpu-timer 2. ? crystal/resonator operation: the on-chip (crystal) oscillator enables the use of an external crystal/resonator attached to the device to provide the time base. the crystal/resonator is connected to the x1/x2 pins. some devices may not have the x1/x2 pins. see table 4-1 for details. ? external clock source operation: if the on-chip (crystal) oscillator is not used, this mode allows it to be bypassed. the device clocks are generated from an external clock source input on the xclkin pin. note that the xclkin is multiplexed with gpio19 or gpio38 pin. the xclkin input can be selected as gpio19 or gpio38 through the xclkinsel bit in xclk register. the clkctl[xclkinoff] bit disables this clock input (forced low). if the clock source is not used or the respective pins are used as gpios, the user should disable at boot time. before changing clock sources, ensure that the target clock is present. if a clock is not present, then that clock source must be disabled (using the clkctl register) before switching clocks. table 6-15. possible pll configuration modes pll mode remarks pllsts[divsel] clkin and sysclkout pll off invoked by the user setting the plloff bit in the pllsts register. the pll block is disabled in this mode. this can be useful to reduce system noise and for low power operation. the pllcr register must first be set to 0x0000 (pll bypass) before entering this mode. the cpu clock (clkin) is derived directly from the input clock on either x1/x2, x1 or xclkin. 0, 1 oscclk/4 2 oscclk/2 3 oscclk/1 pll bypass pll bypass is the default pll configuration upon power-up or after an external reset ( xrs). this mode is selected when the pllcr register is set to 0x0000 or while the pll locks to a new frequency after the pllcr register has been modified. in this mode, the pll itself is bypassed but the pll is not turned off. 0, 1 oscclk/4 2 oscclk/2 3 oscclk/1 pll enable achieved by writing a non-zero value n into the pllcr register. upon writing to the pllcr the device will switch to pll bypass mode until the pll locks. 0, 1 oscclk * n/4 2 oscclk * n/2 3 oscclk * n/1
70 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.6.4 usb and hrcap pll module (pll2) in addition to the main system pll, these devices also contain a second pll (pll2) which can be used to clock the usb and hrcap peripherals. the pll supports multipliers of 1 to 15 and has a fixed divide-by- two on its output. pll2 may be clocked from the following three sources by modifying the pll2clksrcsel bits appropriately in the pll2ctl register: ? intosc1 (internal zero-pin oscillator 1): this is the on-chip internal oscillator 1 and provides a 10- mhz clock. if used as a clock source for hrcap, the oscillator compensation routine should be called frequently. because of accuracy requirements, intosc1 cannot be used as a clock source for the usb. ? crystal/resonator operation: the (crystal) oscillator enables the use of an external crystal or resonator attached to the device to provide the time base. the crystal or resonator is connected to the x1/x2 pins. ? external clock source operation: this mode allows the reference clock to be derived from an external single-ended clock source connected to either gpio19 or gpio38. the xclkinsel bit in the xclk register should be set appropriately to enable the selected gpio to drive xclkin. note for proper operation of the usb module, pll2 should be configured to generate a 120-mhz clock. this will be divided by two to yield the desired 60 mhz for the usb peripheral. hrcap supports a maximum clock input frequency of 120 mhz.
71 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.6.5 loss of input clock (nmi watchdog function) the 2806x devices may be clocked from either one of the internal zero-pin oscillators (intosc1/intosc2), the on-chip crystal oscillator, or from an external clock input. regardless of the clock source, in pll-enabled and pll-bypass mode, if the input clock to the pll vanishes, the pll will issue a limp-mode clock at its output. this limp-mode clock continues to clock the cpu and peripherals at a typical frequency of 1 ? 5 mhz. when the limp mode is activated, a clockfail signal is generated that is latched as an nmi interrupt. depending on how the nmiresetsel bit has been configured, a reset to the device can be fired immediately or the nmi watchdog counter can issue a reset when it overflows. in addition to this, the missing clock status (mclksts) bit is set. the nmi interrupt could be used by the application to detect the input clock failure and initiate necessary corrective action such as switching over to an alternative clock source (if available) or initiate a shut-down procedure for the system. if the software does not respond to the clock-fail condition, the nmi watchdog triggers a reset after a preprogrammed time interval. figure 6-14 shows the interrupt mechanisms involved. figure 6-14. nmi-watchdog 6.6.6 cpu-watchdog module the cpu-watchdog module on the 2806x device is similar to the one used on the 281x/280x/283xx devices. this module generates an output pulse, 512 oscillator clocks wide (oscclk), whenever the 8-bit watchdog up counter has reached its maximum value. to prevent this, the user must disable the counter or the software must periodically write a 0x55 + 0xaa sequence into the watchdog key register that resets the watchdog counter. figure 6-15 shows the various functional blocks within the watchdog module. nmiflg[nmint] 1 0 generate interrupt pulse when input = 1 nmint latch clearset clear nmiflgclr[nmint] xrs 0 nmicfg[clockfail] latch clear set clear xrs nmiflg[clockfail] nmi watchdog sysclkout sysrs nmirs nmiwdprd[15:0] nmiwdcnt[15:0] nmiflgclr[clockfail] sync? nmiflgfrc[clockfail] sysclkout see system control section clockfail
72 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated normally, when the input clocks are present, the cpu-watchdog counter decrements to initiate a cpu- watchdog reset or wdint interrupt. however, when the external input clock fails, the cpu-watchdog counter stops decrementing (that is, the watchdog counter does not change with the limp-mode clock). note the cpu-watchdog is different from the nmi watchdog. the cpu-watchdog is the legacy watchdog that is present in all 28x devices. note applications in which the correct cpu operating frequency is absolutely critical should implement a mechanism by which the mcu will be held in reset, should the input clocks ever fail. for example, an r-c circuit may be used to trigger the xrs pin of the mcu, should the capacitor ever get fully charged. an i/o pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged. such a circuit would also help in detecting failure of the flash memory. a. the wdrst signal is driven low for 512 oscclk cycles. figure 6-15. cpu-watchdog module the wdint signal enables the watchdog to be used as a wakeup from idle/standby mode. in standby mode, all peripherals are turned off on the device. the only peripheral that remains functional is the cpu-watchdog. this module will run off oscclk. the wdint signal is fed to the lpm block so that it can wake the device from standby (if enabled). see section 6.7 for more details. in idle mode, the wdint signal can generate an interrupt to the cpu, through the pie, to take the cpu out of idle mode. in halt mode, the cpu-watchdog can be used to wake up the device through a device reset. /512 wdclk wdcr (wdps[2:0]) wdclk wdcntr(7:0) wdkey(7:0) good key 1 0 1 wdcr (wdchk[2:0]) badwdchk key wdcr (wddis) clear counter scsr (wdenint) watchdog prescaler generate output pulse (512 oscclks) 8-bit watchdog counter clr wdrst wdint watchdog 55 + aa key detector xrs core-reset wdrst (a) internal pullup
73 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) the exit column lists which signals or under what conditions the low power mode is exited. a low signal, on any of the signals, exits the low power condition. this signal must be kept low long enough for an interrupt to be recognized by the device. otherwise, the low-power mode will not be exited and the device will go back into the indicated low power mode. (2) the jtag port can still function even if the cpu clock (clkin) is turned off. (3) the wdclk must be active for the device to go into halt mode. 6.7 low-power modes block table 6-16 summarizes the various modes. table 6-16. low-power modes mode lpmcr0(1:0) oscclk clkin sysclkout exit (1) idle 00 on on on xrs, cpu-watchdog interrupt, any enabled interrupt standby 01 on (cpu-watchdog still running) off off xrs, cpu-watchdog interrupt, gpio port a signal, debugger (2) halt (3) 1x off (on-chip crystal oscillator and pll turned off, zero-pin oscillator and cpu-watchdog state dependent on user code.) off off xrs, gpio port a signal, debugger (2) , cpu-watchdog the various low-power modes operate as follows: idle mode: this mode is exited by any enabled interrupt that is recognized by the processor. the lpm block performs no tasks during this mode as long as the lpmcr0(lpm) bits are set to 0,0. standby mode: any gpio port a signal (gpio[31:0]) can wake the device from standby mode. the user must select which signals will wake the device in the gpiolpmsel register. the selected signals are also qualified by the oscclk before waking the device. the number of oscclks is specified in the lpmcr0 register. halt mode: cpu-watchdog, xrs, and any gpio port a signal (gpio[31:0]) can wake the device from halt mode. the user selects the signal in the gpiolpmsel register. note the low-power modes do not affect the state of the output pins (pwm pins included). they will be in whatever state the code left them in when the idle instruction was executed. see the systems control and interrupts chapter of the tms320x2806x piccolo technical reference manual ( spruh18 ) for more details.
74 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.8 interrupts figure 6-16 shows how the various interrupt sources are multiplexed. figure 6-16. external and pie interrupt sources watchdog xint1 xint1 xint2 gpio mux wdint int1 to int12 nmi low-power modes lpmint wakeint sync sysclkout m u x xint2 m u x xint3 adc xint2soc gpioxint1sel[4:0] gpioxint2sel[4:0] m u x xint3 system control (see the system control section.) int14 int13 gpio0.int gpio31.int dma clear dma pie up to 96 interrupts dma dma tout1 tint0 tint2 tint1 flash wrapper gpioxint3sel[4:0] m u x nmi interrupt with watchdog function (see the nmi watchdog section.) nmirs gpio0.int gpio31.int clockfail cputmr2clk dma c28x core peripherals (usb, mcbsp, epwm, adc) peripherals (spi, sci, i c, ecan, ecap, eqep, hrcap, cla) 2 interrupt control xint1cr[15:0] xint1ctr[15:0] xint2ctr[15:0] interrupt control xint2cr[15:0] interrupt control xint3cr[15:0] xint3ctr[15:0] cpu timer 0 cpu timer 1 cpu timer 2
75 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated eight pie block interrupts are grouped into one cpu interrupt. in total, 12 cpu interrupt groups, with 8 interrupts per group equals 96 possible interrupts. table 6-17 shows the interrupts used by 2806x devices. the trap #vectornumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. trap #0 attempts to transfer program control to the address pointed to by the reset vector. the pie vector table does not, however, include a reset vector. therefore, trap #0 should not be used when the pie is enabled. doing so will result in undefined behavior. when the pie is enabled, trap #1 through trap #12 will transfer program control to the interrupt service routine corresponding to the first vector within the pie group. for example: trap #1 fetches the vector from int1.1, trap #2 fetches the vector from int2.1, and so forth. figure 6-17. multiplexing of interrupts using the pie block int12 mux int11 int2 int1 cpu (enable) (flag) intx intx.8 pieierx[8:1] pieifrx[8:1] mux intx.7 intx.6 intx.5 intx.4 intx.3 intx.2 intx.1 from peripherals or external interrupts (enable) (flag) ier[12:1] ifr[12:1] global enable intm 1 0 pieackx (enable/flag)
76 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) out of 96 possible interrupts, some interrupts are not used. these interrupts are reserved for future devices. these interrupts can be used as software interrupts if they are enabled at the pieifrx level, provided none of the interrupts within the group is being used by a peripheral. otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the pieifr. to summarize, there are two safe cases when the reserved interrupts could be used as software interrupts: ? no peripheral within the group is asserting interrupts. ? no peripheral interrupts are assigned to the group (for example, pie group 7). table 6-17. pie muxed peripheral interrupt vector table (1) intx.8 intx.7 intx.6 intx.5 intx.4 intx.3 intx.2 intx.1 int1.y wakeint tint0 adcint9 xint2 xint1 reserved adcint2 adcint1 (lpm/wd) (timer 0) (adc) ext. int. 2 ext. int. 1 ? (adc) (adc) 0xd4e 0xd4c 0xd4a 0xd48 0xd46 0xd44 0xd42 0xd40 int2.y epwm8_tzint epwm7_tzint epwm6_tzint epwm5_tzint epwm4_tzint epwm3_tzint epwm2_tzint epwm1_tzint (epwm8) (epwm7) (epwm6) (epwm5) (epwm4) (epwm3) (epwm2) (epwm1) 0xd5e 0xd5c 0xd5a 0xd58 0xd56 0xd54 0xd52 0xd50 int3.y epwm8_int epwm7_int epwm6_int epwm5_int epwm4_int epwm3_int epwm2_int epwm1_int (epwm8) (epwm7) (epwm6) (epwm5) (epwm4) (epwm3) (epwm2) (epwm1) 0xd6e 0xd6c 0xd6a 0xd68 0xd66 0xd64 0xd62 0xd60 int4.y hrcap2_int hrcap1_int reserved reserved reserved ecap3_int ecap2_int ecap1_int (hrcap2) (hrcap1) ? ? ? (ecap3) (ecap2) (ecap1) 0xd7e 0xd7c 0xd7a 0xd78 0xd76 0xd74 0xd72 0xd70 int5.y usb0_int reserved reserved hrcap4_int hrcap3_int reserved eqep2_int eqep1_int (usb0) ? ? (hrcap4) (hrcap3) ? (eqep2) (eqep1) 0xd8e 0xd8c 0xd8a 0xd88 0xd86 0xd84 0xd82 0xd80 int6.y reserved reserved mxinta mrinta spitxintb spirxintb spitxinta spirxinta ? ? (mcbsp-a) (mcbsp-a) (spi-b) (spi-b) (spi-a) (spi-a) 0xd9e 0xd9c 0xd9a 0xd98 0xd96 0xd94 0xd92 0xd90 int7.y reserved reserved dintch6 dintch5 dintch4 dintch3 dintch2 dintch1 ? ? (dma) (dma) (dma) (dma) (dma) (dma) 0xdae 0xdac 0xdaa 0xda8 0xda6 0xda4 0xda2 0xda0 int8.y reserved reserved reserved reserved reserved reserved i2cint2a i2cint1a ? ? ? ? ? ? (i2c-a) (i2c-a) 0xdbe 0xdbc 0xdba 0xdb8 0xdb6 0xdb4 0xdb2 0xdb0 int9.y reserved reserved ecan1_inta ecan0_inta scitxintb scirxintb scitxinta scirxinta ? ? (can-a) (can-a) (sci-b) (sci-b) (sci-a) (sci-a) 0xdce 0xdcc 0xdca 0xdc8 0xdc6 0xdc4 0xdc2 0xdc0 int10.y adcint8 adcint7 adcint6 adcint5 adcint4 adcint3 adcint2 adcint1 (adc) (adc) (adc) (adc) (adc) (adc) (adc) (adc) 0xdde 0xddc 0xdda 0xdd8 0xdd6 0xdd4 0xdd2 0xdd0 int11.y cla1_int8 cla1_int7 cla1_int6 cla1_int5 cla1_int4 cla1_int3 cla1_int2 cla1_int1 (cla) (cla) (cla) (cla) (cla) (cla) (cla) (cla) 0xdee 0xdec 0xdea 0xde8 0xde6 0xde4 0xde2 0xde0 int12.y luf lvf reserved reserved reserved reserved reserved xint3 (cla) (cla) ? ? ? ? ? ext. int. 3 0xdfe 0xdfc 0xdfa 0xdf8 0xdf6 0xdf4 0xdf2 0xdf0
77 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) the pie configuration and control registers are not protected by eallow mode. the pie vector table is protected. table 6-18. pie configuration and control registers name address size ( 16) description (1) piectrl 0x0ce0 1 pie, control register pieack 0x0ce1 1 pie, acknowledge register pieier1 0x0ce2 1 pie, int1 group enable register pieifr1 0x0ce3 1 pie, int1 group flag register pieier2 0x0ce4 1 pie, int2 group enable register pieifr2 0x0ce5 1 pie, int2 group flag register pieier3 0x0ce6 1 pie, int3 group enable register pieifr3 0x0ce7 1 pie, int3 group flag register pieier4 0x0ce8 1 pie, int4 group enable register pieifr4 0x0ce9 1 pie, int4 group flag register pieier5 0x0cea 1 pie, int5 group enable register pieifr5 0x0ceb 1 pie, int5 group flag register pieier6 0x0cec 1 pie, int6 group enable register pieifr6 0x0ced 1 pie, int6 group flag register pieier7 0x0cee 1 pie, int7 group enable register pieifr7 0x0cef 1 pie, int7 group flag register pieier8 0x0cf0 1 pie, int8 group enable register pieifr8 0x0cf1 1 pie, int8 group flag register pieier9 0x0cf2 1 pie, int9 group enable register pieifr9 0x0cf3 1 pie, int9 group flag register pieier10 0x0cf4 1 pie, int10 group enable register pieifr10 0x0cf5 1 pie, int10 group flag register pieier11 0x0cf6 1 pie, int11 group enable register pieifr11 0x0cf7 1 pie, int11 group flag register pieier12 0x0cf8 1 pie, int12 group enable register pieifr12 0x0cf9 1 pie, int12 group flag register reserved 0x0cfa ? 0x0cff 6 reserved
78 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.8.1 external interrupts table 6-19. external interrupt registers name address size ( 16) description xint1cr 0x00 7070 1 xint1 configuration register xint2cr 0x00 7071 1 xint2 configuration register xint3cr 0x00 7072 1 xint3 configuration register xint1ctr 0x00 7078 1 xint1 counter register xint2ctr 0x00 7079 1 xint2 counter register xint3ctr 0x00 707a 1 xint3 counter register each external interrupt can be enabled or disabled or qualified using positive, negative, or both positive and negative edge. for more information, see the systems control and interrupts chapter of the tms320x2806x piccolo technical reference manual ( spruh18 ). 6.8.1.1 external interrupt electrical data/timing (1) for an explanation of the input qualifier parameters, see table 6-76 . (2) this timing is applicable to any gpio pin configured for adcsoc functionality. table 6-20. external interrupt timing requirements (1) min max unit t w(int) (2) pulse duration, int input low/high synchronous 1t c(sco) cycles with qualifier 1t c(sco) + t w(iqsw) cycles (1) for an explanation of the input qualifier parameters, see table 6-76 . table 6-21. external interrupt switching characteristics (1) over recommended operating conditions (unless otherwise noted) parameter min max unit t d(int) delay time, int low/high to interrupt-vector fetch t w(iqsw) + 12t c(sco) cycles figure 6-18. external interrupt timing xint1, xint2, xint3 t w(int) interrupt vector t d(int) address bus (internal)
79 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9 peripherals 6.9.1 control law accelerator (cla) overview the control law accelerator extends the capabilities of the c28x cpu by adding parallel processing. time- critical control loops serviced by the cla can achieve low adc sample to output delay. thus, the cla enables faster system response and higher frequency control loops. using the cla for time-critical tasks frees up the main cpu to perform other system and communication functions concurently. the following is a list of major features of the cla. ? clocked at the same rate as the main cpu (sysclkout). ? an independent architecture allowing cla algorithm execution independent of the main c28x cpu. ? complete bus architecture: ? program address bus and program data bus ? data address bus, data read bus, and data write bus ? independent eight-stage pipeline. ? 12-bit program counter (mpc) ? four 32-bit result registers (mr0 ? mr3) ? two 16-bit auxillary registers (mar0, mar1) ? status register (mstf) ? instruction set includes: ? ieee single-precision (32-bit) floating-point math operations ? floating-point math with parallel load or store ? floating-point multiply with parallel add or subtract ? 1/x and 1/sqrt(x) estimations ? data type conversions. ? conditional branch and call ? data load and store operations ? the cla program code can consist of up to eight tasks or interrupt service routines. ? the start address of each task is specified by the mvect registers. ? no limit on task size as long as the tasks fit within the cla program memory space. ? one task is serviced at a time through to completion. there is no nesting of tasks. ? upon task completion, a task-specific interrupt is flagged within the pie. ? when a task finishes, the next highest-priority pending task is automatically started. ? task trigger mechanisms: ? c28x cpu through the iack instruction ? task1 to task7: the corresponding adc, epwm, eqep, or ecap module interrupt. for example: ? task1: adcint1 or epwm1_int ? task2: adcint2 or epwm2_int ? task4: adcint4 or epwm4_int or eqepx_int or ecapx_int ? task7: adcint7 or epwm7_int or eqepx_int or ecapx_int ? task8: adcint8 or by cpu timer 0 or eqepx_int or ecapx_int. ? memory and shared peripherals: ? two dedicated message rams for communication between the cla and the main cpu. ? the c28x cpu can map cla program and data memory to the main cpu space or cla space. ? the cla has direct access to the adc result registers, comparator registers, and the ecap, eqep, and epwm+hrpwm registers.
80 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated figure 6-19. cla block diagram cla_int1 to cla_int8 mvect1 mvect2 mperint1 to mperint8 pie main 28x cpu cla program memory mmemcfg mctl mifr mier mifrc mirun miovf miclr miclrovf mpisrcsel1 mvect3 mvect4 mvect5 mvect6 mvect7 mvect8 ain cpu bus int11 int12 peripheral interrupts adcint1 to adcint8 ecap1_int to ecap3_int eqep1_int and eqep2_int epwm1_int to epwm8_int cpu timer 0 map to cla or cpu space cla data memory comparator registers ecap registers eqep registers epwm and hrpwm registers adc result registers cla shared message rams main cpu read/write data bus cla program address bus cla program data bus map to cla or cpu space cla data bus main cpu bus mr0(32) mpc(12) mr1(32) mr3(32) mar0(32) mstf(32) mr2(32) mar1(32) cla data read address bus cla data write data bus cla data write address bus cla data read data bus meallow main cpu read data bus cla execution registers cla control registers sysclkout claenclk sysrs lvf luf iack
81 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) all registers in this table are csm protected (2) the main c28x cpu has read only access to this register for debug purposes. the main cpu cannot perform cpu or debugger writes to this register. table 6-22. cla control registers register name cla1 address size ( 16) eallow protected description (1) mvect1 0x1400 1 yes cla interrupt/task 1 start address mvect2 0x1401 1 yes cla interrupt/task 2 start address mvect3 0x1402 1 yes cla interrupt/task 3 start address mvect4 0x1403 1 yes cla interrupt/task 4 start address mvect5 0x1404 1 yes cla interrupt/task 5 start address mvect6 0x1405 1 yes cla interrupt/task 6 start address mvect7 0x1406 1 yes cla interrupt/task 7 start address mvect8 0x1407 1 yes cla interrupt/task 8 start address mctl 0x1410 1 yes cla control register mmemcfg 0x1411 1 yes cla memory configure register mpisrcsel1 0x1414 2 yes peripheral interrupt source select register 1 mifr 0x1420 1 yes interrupt flag register miovf 0x1421 1 yes interrupt overflow register mifrc 0x1422 1 yes interrupt force register miclr 0x1423 1 yes interrupt clear register miclrovf 0x1424 1 yes interrupt overflow clear register mier 0x1425 1 yes interrupt enable register mirun 0x1426 1 yes interrupt run register mipctl 0x1427 1 yes interrupt priority control register mpc (2) 0x1428 1 ? cla program counter mar0 (2) 0x142a 1 ? cla aux register 0 mar1 (2) 0x142b 1 ? cla aux register 1 mstf (2) 0x142e 2 ? cla stf register mr0 (2) 0x1430 2 ? cla r0h register mr1 (2) 0x1434 2 ? cla r1h register mr2 (2) 0x1438 2 ? cla r2h register mr3 (2) 0x143c 2 ? cla r3h register table 6-23. cla message ram address range size ( 16) description 0x1480 ? 0x14ff 128 cla to cpu message ram 0x1500 ? 0x157f 128 cpu to cla message ram
82 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.2 analog block a 12-bit adc core is implemented that has different timings than the 12-bit adc used on the f280x and f2833x devices. the adc wrapper is modified to incorporate the new timings and also other enhancements to improve the timing control of start of conversions. figure 6-20 shows the interaction of the analog module with the rest of the f2806x system. figure 6-20. analog pin configurations 100-pin 80-pin vdda vdda vreflo tied to vssa vssa vreflo vrefhi a0 vrefhi tied to a0 a1 a2 a1 a2 a3 a4 a4 a5 a6 a6 a7 b0 b0 b1 b1 b2 b2 b3 b4 b4 b5 b6 b6 b7 (3.3 v) vdda (agnd) vssa vreflo diff interface reference comp1 vrefhi a0b0 aio2 aio10 a1b1 10-bit dac a2 b2 comp1out a3b3 aio4 aio12 a4 b4 comp2 10-bit dac comp2out comp3 10-bit dac comp3out adc b5 a5 aio6 aio14 a6 b6 a7b7 simultaneous sampling channels signal pinout temperature sensor a5b5
83 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.2.1 analog-to-digital converter (adc) 6.9.2.1.1 features the core of the adc contains a single 12-bit converter fed by two sample-and-hold circuits. the sample- and-hold circuits can be sampled simultaneously or sequentially. these, in turn, are fed by a total of up to 16 analog input channels. the converter can be configured to run with an internal bandgap reference to create true-voltage based conversions or with a pair of external voltage references (v refhi /v reflo ) to create ratiometric-based conversions. contrary to previous adc types, this adc is not sequencer-based. the user can easily create a series of conversions from a single trigger. however, the basic principle of operation is centered around the configurations of individual conversions, called socs, or start-of-conversions. functions of the adc module include: ? 12-bit adc core with built-in dual sample-and-hold (s/h) ? simultaneous sampling or sequential sampling modes ? full range analog input: 0 v to 3.3 v fixed, or v refhi /v reflo ratiometric. the digital value of the input analog voltage is derived by: ? internal reference (v reflo = v ssa . v refhi must not exceed v dda when using either internal or external reference modes.) ? external reference (v refhi /v reflo connected to external references. v refhi must not exceed v dda when using either internal or external reference modes.) ? up to 16-channel, multiplexed inputs ? 16 socs, configurable for trigger, sample window, and channel ? 16 result registers (individually addressable) to store conversion values ? multiple trigger sources ? s/w ? software immediate start ? epwm 1 ? 8 ? gpio xint2 ? cpu timer 0, cpu timer 1, cpu timer 2 ? adcint1, adcint2 ? 9 flexible pie interrupts, can configure interrupt request after any conversion 0, value digital = v0 input when v v v voltage analog input 4096 value digital reflo refhi reflo - - = v input v0 when refhi < < 4095, value digital = v input when refhi 3 0, value digital = v0 input when 3.3 v voltage analog input 4096 value digital reflo - = v 3.3 input v0 when < < 4095, value digital = v 3.3 input when 3
84 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated table 6-24. adc configuration and control registers register name address size ( 16) eallow protected description adcctl1 0x7100 1 yes control 1 register adcctl2 0x7101 1 yes control 2 register adcintflg 0x7104 1 no interrupt flag register adcintflgclr 0x7105 1 no interrupt flag clear register adcintovf 0x7106 1 no interrupt overflow register adcintovfclr 0x7107 1 no interrupt overflow clear register intsel1n2 0x7108 1 yes interrupt 1 and 2 selection register intsel3n4 0x7109 1 yes interrupt 3 and 4 selection register intsel5n6 0x710a 1 yes interrupt 5 and 6 selection register intsel7n8 0x710b 1 yes interrupt 7 and 8 selection register intsel9n10 0x710c 1 yes interrupt 9 selection register (reserved interrupt 10 selection) socprictl 0x7110 1 yes soc priority control register adcsamplemode 0x7112 1 yes sampling mode register adcintsocsel1 0x7114 1 yes interrupt soc selection 1 register (for 8 channels) adcintsocsel2 0x7115 1 yes interrupt soc selection 2 register (for 8 channels) adcsocflg1 0x7118 1 no soc flag 1 register (for 16 channels) adcsocfrc1 0x711a 1 no soc force 1 register (for 16 channels) adcsocovf1 0x711c 1 no soc overflow 1 register (for 16 channels) adcsocovfclr1 0x711e 1 no soc overflow clear 1 register (for 16 channels) adcsoc0ctl to adcsoc15ctl 0x7120 ? 0x712f 1 yes soc0 control register to soc15 control register adcreftrim 0x7140 1 yes reference trim register adcofftrim 0x7141 1 yes offset trim register comphystctl 0x714c 1 yes comparator hysteresis control register adcrev 0x714f 1 no revision register table 6-25. adc result registers (mapped to pf0) register name address size ( 16) eallow protected description adcresult0 to adcresult15 0xb00 ? 0xb0f 1 no adc result 0 register to adc result 15 register
85 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated figure 6-21. adc connections adc connections if the adc is not used it is recommended that the connections for the analog power pins be kept, even if the adc is not used. following is a summary of how the adc pins should be connected, if the adc is not used in an application: ? v dda ? connect to v ddio ? v ssa ? connect to v ss ? v reflo ? connect to v ss ? adcinan, adcinbn, v refhi ? connect to v ssa when the adc module is used in an application, unused adc input pins should be connected to analog ground (v ssa ). note: unused adcin pins that are multiplexed with aio function should not be directly connected to analog ground. they should be grounded through a 1-k resistor. this is to prevent an errant code from configuring these pins as aio outputs and driving grounded pins to a logic-high state. when the adc is not used, be sure that the clock to the adc module is not turned on to realize power savings. pf0 (cpu) pf2 (cpu) sysclkout adcenclk aio mux adc channels adc core 12-bit 0-wait result registers adcint 1 adcint 9 adctrig 1 tint 0 pie cputimer 0 adctrig 2 tint 1 cputimer 1 adctrig 3 tint 2 cputimer 2 adctrig 4 xint 2soc xint 2 adctrig 5 soca 1 epwm 1 adctrig 6 socb 1 adctrig 7 soca 2 epwm 2 adctrig 8 socb 2 adctrig 9 soca 3 epwm 3 adctrig 10 socb 3 adctrig 11 soca 4 epwm 4 adctrig 12 socb 4 adctrig 13 soca 5 epwm 5 adctrig 14 socb 5 adctrig 15 soca 6 epwm 6 adctrig 16 socb 6 adctrig 17 soca 7 epwm 7 adctrig 18 socb 7 adctrig 19 soca 8 epwm 8 adctrig 20 socb 8
86 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.2.1.2 adc start-of-conversion electrical data/timing table 6-26. external adc start-of-conversion switching characteristics over recommended operating conditions (unless otherwise noted) parameter min max unit t w(adcsocl) pulse duration, adcsocxo low 32t c(hco) cycles (1) inl will degrade when the adc input voltage goes above v dda . (2) 1 lsb has the weighted value of full-scale range (fsr)/4096. fsr is 3.3 v with internal reference and v refhi - v reflo for external reference. (3) for more details, see the tms320f28069, tms320f28068, tms320f28067, tms320f28066, tms320f28065, tms320f28064, tms320f28063, tms320f28062 piccolo mcus silicon errata ( sprz342 ). (4) periodic self-recalibration will remove system-level and temperature dependencies on the adc zero offset error. (5) v reflo is always connected to v ssa on the 80-pin pn and pfp devices. (6) v refhi must not exceed v dda when using either internal or external reference modes. since v refhi is tied to adcina0 on the 80-pin pn and pfp devices, the input signal on adcina0 must not exceed v dda . figure 6-22. adcsocao or adcsocbo timing 6.9.2.1.3 on-chip analog-to-digital converter (adc) electrical data/timing table 6-27. adc electrical characteristics parameter min typ max unit dc specifications resolution 12 bits adc clock 90-mhz device 0.001 45 mhz sample window 7 64 adc clocks accuracy inl (integral nonlinearity) (1) ? 4 4 lsb dnl (differential nonlinearity), no missing codes ? 1 1.5 lsb offset error (2) executing a single self- recalibration (3) ? 20 20 lsb executing periodic self- recalibration (4) ? 4 4 overall gain error with internal reference ? 60 60 lsb overall gain error with external reference ? 40 40 lsb channel-to-channel offset variation ? 4 4 lsb channel-to-channel gain variation ? 4 4 lsb adc temperature coefficient with internal reference ? 50 ppm/ c adc temperature coefficient with external reference ? 20 ppm/ c v reflo ? 100 a v refhi 100 a analog input analog input voltage with internal reference 0 3.3 v analog input voltage with external reference v reflo v refhi v v reflo input voltage (5) v ssa 0.66 v v refhi input voltage (6) 2.64 v dda v with v reflo = v ssa 1.98 v dda input capacitance 5 pf input leakage current 2 a adcsocaoadcsocbo or t w(adcsocl)
87 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated table 6-28. adc power modes adc operating mode conditions i dda unit mode a ? operating mode adc clock enabled bandgap on (adcbgpwd = 1) reference on (adcrefpwd = 1) adc powered up (adcpwdn = 1) 16 ma mode b ? quick wake mode adc clock enabled bandgap on (adcbgpwd = 1) reference on (adcrefpwd = 1) adc powered up (adcpwdn = 0) 4 ma mode c ? comparator-only mode adc clock enabled bandgap on (adcbgpwd = 1) reference on (adcrefpwd = 0) adc powered up (adcpwdn = 0) 1.5 ma mode d ? off mode adc clock enabled bandgap on (adcbgpwd = 0) reference on (adcrefpwd = 0) adc powered up (adcpwdn = 0) 0.075 ma (1) the temperature sensor slope and offset are given in terms of adc lsbs using the internal reference of the adc. values must be adjusted accordingly in external reference mode to the external reference voltage. (2) adc temperature coeffieicient is accounted for in this specification (3) output of the temperature sensor (in terms of lsbs) is sign-consistent with the direction of the temperature movement. increasing temperatures will give increasing adc values relative to an initial value; decreasing temperatures will give decreasing adc values relative to an initial value. 6.9.2.1.3.1 internal temperature sensor table 6-29. temperature sensor coefficient parameter (1) min typ max unit t slope degrees c of temperature movement per measured adc lsb change of the temperature sensor 0.18 (2) (3) c/lsb t offset adc output at 0 c of the temperature sensor 1750 lsb (1) timings maintain compatibility to the adc module. the 2806x adc supports driving all 3 bits at the same time t d(pwd) ms before first conversion. 6.9.2.1.3.2 adc power-up control bit timing table 6-30. adc power-up delays parameter (1) min max unit t d(pwd) delay time for the adc to be stable after power up 1 ms figure 6-23. adc conversion timing adcpwdn/ adcbgpwd/ adcrefpwd/ adcenable request for adc conversion t d(pwd)
88 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated figure 6-24. adc input impedance model ac r s adcin c 5 pf p c 1.6 pf h switch typical values of the input circuit components: switch resistance (r ): 3.4 k on w sampling capacitor (c ): 1.6 pf h parasitic capacitance (c ): 5 pf p source resistance (r ): 50 s w 28x dsp source signal 3.4 k w r on
89 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.2.1.3.3 adc sequential and simultaneous timings figure 6-25. timing example for sequential mode / late interrupt pulse soc0 adcclk adcresult 0 s/h window pulse to core adcctl 1.intpulsepos adcsocflg 1.soc0 adcintflg .adcintx soc1 soc2 9 15 22 24 37 2 0 result 0 latched adcsocflg 1.soc1 adcsocflg 1.soc2 adcresult 1 eoc0 pulse eoc1 pulse conversion 0 13 adc clocks minimum 7 adcclks 6 adcclks conversion 1 13 adc clocks minimum 7 adcclks 2 adcclks 1 adcclk analog input soc1 sample window soc0 sample window soc2 sample window
90 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated figure 6-26. timing example for sequential mode / early interrupt pulse conversion 0 13 adc clocks minimum 7 adcclks soc0 adcclk adcresult 0 s/h window pulse to core adcctl1.intpulsepos adcsocflg 1.soc0 adcintflg .adcintx soc1 soc2 9 15 22 24 37 6 adcclks 2 0 result 0 latched conversion 1 13 adc clocks minimum 7 adcclks adcsocflg 1.soc1 adcsocflg 1.soc2 adcresult 1 eoc0 pulse eoc1 pulse eoc2 pulse 2 adcclks analog input soc1 sample window soc0 sample window soc2 sample window
91 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated figure 6-27. timing example for simultaneous mode / late interrupt pulse conversion 0 (a) 13 adc clocks minimum 7 adcclks soc0 (a/b) adcclk adcresult 0 s/h window pulse to core adcctl1.intpulsepos adcsocflg 1.soc0 adcintflg .adcintx soc2 (a/b) 9 22 24 37 19 adcclks 20 result 0 (a) latched conversion 0 (b) 13 adc clocks minimum 7 adcclks adcsocflg 1.soc1 adcsocflg 1.soc2 adcresult 1 result 0 (b) latched conversion 1 (a) 13 adc clocks adcresult 2 50 eoc0 pulse eoc1 pulse eoc2 pulse 1 adcclk 2 adcclks 2 adcclks analog input b soc0 sample b window soc2 sample b window analog input a soc0 sample a window soc2 sample a window
92 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated figure 6-28. timing example for simultaneous mode / early interrupt pulse adcclk 2 0 9 soc0 sample b window analog input b analog input a soc0 sample a window 37 50 soc2 sample b window soc2 sample a window 24 22 adcctl1.intpulsepos adcsocflg1.soc0 adcsocflg1.soc1 adcsocflg1.soc2 s/h window pulse to core soc0 (a/b) soc2 (a/b) adcresult 0 result 0 (a) latched 2 adcclks result 0 (b) latched adcresult 1 adcresult 2 eoc0 pulse eoc1 pulse eoc2 pulse minimum 7 adcclks conversion 0 (a) 13 adc clocks 2 adcclks minimum 7 adcclks conversion 1 (a) 13 adc clocks conversion 0 (b) 13 adc clocks adcintflg.adcintx 19 adcclks
93 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.2.2 adc mux figure 6-29. aiox pin multiplexing the adc channel and comparator functions are always available. the digital i/o function is available only when the respective bit in the aiomux1 register is 0. in this mode, reading the aiodat register reflects the actual pin state. the digital i/o function is disabled when the respective bit in the aiomux1 register is 1. in this mode, reading the aiodat register reflects the output latch of the aiodat register and the input digital i/o buffer is disabled to prevent analog signals from generating noise. on reset, the digital function is disabled. if the pin is used as an analog input, users should keep the aio function disabled for that pin. to compy a or b input to adc channel x 1 0 aiox pin aioxin aioxine sync sysclk logic implemented in gpio mux block aiodat reg (read) aiodat reg (latch) aioset, aioclear, aiotoggle regs aiomux 1 reg 1 0 aioxdir (1 = input, 0 = output) (0 = input, 1 = output) aiodir reg (latch) 0
94 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.2.3 comparator block figure 6-30 shows the interaction of the comparator modules with the rest of the system. figure 6-30. comparator block diagram table 6-31. comparator control registers register name comp1 address comp2 address comp3 address size ( 16) eallow protected description compctl 0x6400 0x6420 0x6440 1 yes comparator control register compsts 0x6402 0x6422 0x6442 1 no comparator status register dacctl 0x6404 0x6424 0x6444 1 yes dac control register dacval 0x6406 0x6426 0x6446 1 no dac value register rampmaxref_ active 0x6408 0x6428 0x6448 1 no ramp generator maximum reference (active) register rampmaxref_ shdw 0x640a 0x642a 0x644a 1 no ramp generator maximum reference (shadow) register rampdecval_ active 0x640c 0x642c 0x644c 1 no ramp generator decrement value (active) register rampdecval_ shdw 0x640e 0x642e 0x644e 1 no ramp generator decrement value (shadow) register rampsts 0x6410 0x6430 0x6450 1 no ramp generator status register aio mux comp x a comp x b comp x + dac x wrapper dac core 10-bit + - comp compxout gpio mux tz1/2/3 epwm
95 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) hysteresis on the comparator inputs is achieved with a schmidt trigger configuration. this results in an effective 100-k feedback resistance between the output of the comparator and the non-inverting input of the comparator. 6.9.2.3.1 on-chip comparator/dac electrical data/timing table 6-32. electrical characteristics of the comparator/dac characteristic min typ max unit comparator comparator input range v ssa ? v dda v comparator response time to pwm trip zone (async) 30 ns input offset 5 mv input hysteresis (1) 35 mv dac dac output range v ssa ? v dda v dac resolution 10 bits dac settling time see figure 6-31 dac gain ? 1.5% dac offset 10 mv monotonic yes inl 3 lsb figure 6-31. dac settling time settling time (ns) 0 100 200 300 400 500 600 700 800 900 1000 1100 0 50 100 150 200 250 300 350 400 450 500 dac step size (codes) 15 codes 7 codes 3 codes 1 code dac accuracy
96 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.3 detailed descriptions integral nonlinearity integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. the point used as zero occurs one-half lsb before the first code transition. the full-scale point is defined as level one-half lsb beyond the last code transition. the deviation is measured from the center of each particular code to the true straight line between these two points. differential nonlinearity an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. a differential nonlinearity error of less than 1 lsb ensures no missing codes. zero offset the major carry transition should occur when the analog input is at zero volts. zero error is defined as the deviation of the actual transition from that point. gain error the first code transition should occur at an analog value one-half lsb above negative full scale. the last transition should occur at an analog value one and one-half lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. signal-to-noise ratio + distortion (sinad) sinad is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. effective number of bits (enob) for a sine wave, sinad can be expressed in terms of the number of bits. using the following formula, it is possible to get a measure of performance expressed as n, the effective number of bits. thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad. total harmonic distortion (thd) thd is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. spurious free dynamic range (sfdr) sfdr is the difference in db between the rms amplitude of the input signal and the peak spurious signal. 6.02 1.76) (sinad n - =
97 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.4 serial peripheral interface (spi) module the device includes the four-pin serial peripheral interface (spi) module. up to two spi modules are available. the spi is a high-speed, synchronous serial i/o port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. normally, the spi is used for communications between the mcu and external peripherals or another processor. typical applications include external i/o or peripheral expansion through devices such as shift registers, display drivers, and adcs. multidevice communications are supported by the master/slave operation of the spi. the spi module features include: ? four external pins: ? spisomi: spi slave-output/master-input pin ? spisimo: spi slave-input/master-output pin ? spiste: spi slave transmit-enable pin ? spiclk: spi serial-clock pin note: all four pins can be used as gpio if the spi module is not used. ? two operational modes: master and slave baud rate: 125 different programmable rates. ? data word length: 1 to 16 data bits ? four clocking schemes (controlled by clock polarity and clock phase bits) include: ? falling edge without phase delay: spiclk active-high. spi transmits data on the falling edge of the spiclk signal and receives data on the rising edge of the spiclk signal. ? falling edge with phase delay: spiclk active-high. spi transmits data one half-cycle ahead of the falling edge of the spiclk signal and receives data on the falling edge of the spiclk signal. ? rising edge without phase delay: spiclk inactive-low. spi transmits data on the rising edge of the spiclk signal and receives data on the falling edge of the spiclk signal. ? rising edge with phase delay: spiclk inactive-low. spi transmits data one half-cycle ahead of the falling edge of the spiclk signal and receives data on the rising edge of the spiclk signal. ? simultaneous receive and transmit operation (transmit function can be disabled in software) ? transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. ? nine spi module control registers: located in control register frame beginning at address 7040h. note all registers in this module are 16-bit registers that are connected to peripheral frame 2. when a register is accessed, the register data is in the lower byte (7 ? 0), and the upper byte (15 ? 8) is read as zeros. writing to the upper byte has no effect. enhanced feature: ? 4-level transmit/receive fifo ? delayed transmit control ? bi-directional 3 wire spi mode support ? audio data receive support through spiste inversion 1) (spibrr lspclk rate baud + = 127 to3 spibrr when = 4 lspclk rate baud = 21, 0, spibrr when =
98 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) registers in this table are mapped to peripheral frame 2. this space only allows 16-bit accesses. 32-bit accesses produce undefined results. the spi port operation is configured and controlled by the registers listed in table 6-33 and table 6-34 . table 6-33. spi-a registers name address size ( 16) eallow protected description (1) spiccr 0x7040 1 no spi-a configuration control register spictl 0x7041 1 no spi-a operation control register spists 0x7042 1 no spi-a status register spibrr 0x7044 1 no spi-a baud rate register spirxemu 0x7046 1 no spi-a receive emulation buffer register spirxbuf 0x7047 1 no spi-a serial input buffer register spitxbuf 0x7048 1 no spi-a serial output buffer register spidat 0x7049 1 no spi-a serial data register spifftx 0x704a 1 no spi-a fifo transmit register spiffrx 0x704b 1 no spi-a fifo receive register spiffct 0x704c 1 no spi-a fifo control register spipri 0x704f 1 no spi-a priority control register (1) registers in this table are mapped to peripheral frame 2. this space only allows 16-bit accesses. 32-bit accesses produce undefined results. table 6-34. spi-b registers name address size ( 16) eallow protected description (1) spiccr 0x7740 1 no spi-b configuration control register spictl 0x7741 1 no spi-b operation control register spists 0x7742 1 no spi-b status register spibrr 0x7744 1 no spi-b baud rate register spirxemu 0x7746 1 no spi-b receive emulation buffer register spirxbuf 0x7747 1 no spi-b serial input buffer register spitxbuf 0x7748 1 no spi-b serial output buffer register spidat 0x7749 1 no spi-b serial data register spifftx 0x774a 1 no spi-b fifo transmit register spiffrx 0x774b 1 no spi-b fifo receive register spiffct 0x774c 1 no spi-b fifo control register spipri 0x774f 1 no spi-b priority control register
99 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated figure 6-32 is a block diagram of the spi in slave mode. a. spiste is driven low by the master for a slave device. figure 6-32. spi module block diagram (slave mode) s spictl.0 spi int flag spi int ena spists.6 s clock polarity talk lspclk spi bit rate state control clock phase receiver overrun flag spictl.4 overrun int ena spiccr.3 - 0 spibrr.6 - 0 spiccr.6 spictl.3 spidat.15 - 0 spictl.1 m s m master/slave spists.7 spidat data register m s spictl.2 spi char spisimo spisomi spiclk sw2 s m m s sw3 to cpu m sw1 rx fifo _0rx fifo _1 ----- rx fifo _3 tx fifo registers tx fifo _0 tx fifo _1 ----- tx fifo _3 rx fifo registers 16 16 16 tx interrupt logic rx interrupt logic spiint spitx spiffovf flag spiffrx.15 tx fifo interrupt rx fifo interrupt spirxbuf spitxbuf spifftx.14 spiffena spiste 16 0 12 3 0 12 3 4 5 6 tw tw tw spipri.0 triwire spipri.1 steinv steinv spirxbuf buffer register spitxbuf buffer register
copyright ? 2010 ? 2016, texas instruments incorporated detailed description submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 100 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com 6.9.4.1 spi master mode electrical data/timing table 6-35 lists the master mode timing (clock phase = 0) and table 6-36 lists the master mode timing (clock phase = 1). figure 6-33 and figure 6-34 show the timing waveforms. (1) the master/slave bit (spictl.2) is set and the clock phase bit (spictl.3) is cleared. (2) t c(spc) = spi clock cycle time = lspclk/4 or lspclk/(spibrr +1) (3) t c(lco) = lspclk cycle time (4) internal clock prescalers must be adjusted such that the spi clock speed is limited to the following spi clock rate: master mode transmit 20-mhz max, master mode receive 10-mhz max slave mode transmit 10-mhz max, slave mode receive 10-mhz max. (5) the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spiccr.6). table 6-35. spi master mode external timing (clock phase = 0) (1) (2) (3) (4) (5) no. spi when (spibrr + 1) is even or spibrr = 0 or 2 spi when (spibrr + 1) is odd and spibrr > 3 unit min max min max 1 t c(spc)m cycle time, spiclk 4t c(lco) 128t c(lco) 5t c(lco) 127t c(lco) ns 2 t w(spch)m pulse duration, spiclk high (clock polarity = 0) 0.5t c(spc)m ? 10 0.5t c(spc)m 0.5t c(spc)m ? 0.5t c(lco) ? 10 0.5t c(spc)m ? 0.5t c(lco) ns t w(spcl)m pulse duration, spiclk low (clock polarity = 1) 0.5t c(spc)m ? 10 0.5t c(spc)m 0.5t c(spc)m ? 0.5t c(lco) ? 10 0.5t c(spc)m ? 0.5t c(lco) 3 t w(spcl)m pulse duration, spiclk low (clock polarity = 0) 0.5t c(spc)m ? 10 0.5 tc(spc)m 0.5t c(spc)m + 0.5t c(lco) ? 10 0.5t c(spc)m + 0.5t c(lco) ns t w(spch)m pulse duration, spiclk high (clock polarity = 1) 0.5 tc(spc)m ? 10 0.5t c(spc)m 0.5t c(spc)m + 0.5t c(lco) ? 10 0.5t c(spc)m + 0.5t c(lco) 4 t d(spch-simo)m delay time, spiclk high to spisimo valid (clock polarity = 0) 10 10 ns t d(spcl-simo)m delay time, spiclk low to spisimo valid (clock polarity = 1) 10 10 5 t v(spcl-simo)m valid time, spisimo data valid after spiclk low (clock polarity = 0) 0.5t c(spc)m ? 10 0.5t c(spc)m + 0.5t c(lco) ? 10 ns t v(spch-simo)m valid time, spisimo data valid after spiclk high (clock polarity = 1) 0.5t c(spc)m ? 10 0.5t c(spc)m + 0.5t c(lco) ? 10 8 t su(somi-spcl)m setup time, spisomi before spiclk low (clock polarity = 0) 26 26 ns t su(somi-spch)m setup time, spisomi before spiclk high (clock polarity = 1) 26 26 9 t v(spcl-somi)m valid time, spisomi data valid after spiclk low (clock polarity = 0) 0.25t c(spc)m ? 10 0.5t c(spc)m ? 0.5t c(lco) ? 10 ns t v(spch-somi)m valid time, spisomi data valid after spiclk high (clock polarity = 1) 0.25t c(spc)m ? 10 0.5t c(spc)m ? 0.5t c(lco) ? 10
copyright ? 2010 ? 2016, texas instruments incorporated detailed description submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 101 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 a. in the master mode, spiste goes active 0.5t c(spc) (minimum) before valid spi clock edge. on the trailing end of the word, the spiste will go inactive 0.5t c(spc) after the receiving edge (spiclk) of the last data bit, except that spiste stays active between back-to-back transmit words in both fifo and non-fifo modes. figure 6-33. spi master mode external timing (clock phase = 0) 9 4 spisomi spisimo spiclk (clock polarity = 1) spiclk (clock polarity = 0) master in data must be valid master out data is valid spiste (a) 1 2 3 5 8
copyright ? 2010 ? 2016, texas instruments incorporated detailed description submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 102 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com (1) the master/slave bit (spictl.2) is set and the clock phase bit (spictl.3) is set. (2) t c(spc) = spi clock cycle time = lspclk/4 or lspclk/(spibrr + 1) (3) internal clock prescalers must be adjusted such that the spi clock speed is limited to the following spi clock rate: master mode transmit 20-mhz max, master mode receive 10-mhz max slave mode transmit 10-mhz max, slave mode receive 10-mhz max. (4) t c(lco) = lspclk cycle time (5) the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spiccr.6). table 6-36. spi master mode external timing (clock phase = 1) (1) (2) (3) (4) (5) no. spi when (spibrr + 1) is even or spibrr = 0 or 2 spi when (spibrr + 1) is odd and spibrr > 3 unit min max min max 1 t c(spc)m cycle time, spiclk 4t c(lco) 128t c(lco) 5t c(lco) 127t c(lco) ns 2 t w(spch)m pulse duration, spiclk high (clock polarity = 0) 0.5t c(spc)m ? 10 0.5t c(spc)m 0.5t c(spc)m ? 0.5t c (lco) ? 10 0.5t c(spc)m ? 0.5t c(lco) ns t w(spcl))m pulse duration, spiclk low (clock polarity = 1) 0.5t c(spc)m ? 10 0.5t c(spc)m 0.5t c(spc)m ? 0.5t c (lco) ? 10 0.5t c(spc)m ? 0.5t c(lco 3 t w(spcl)m pulse duration, spiclk low (clock polarity = 0) 0.5t c(spc)m ? 10 0.5t c(spc)m 0.5t c(spc)m + 0.5t c(lco) ? 10 0.5t c(spc)m + 0.5t c(lco) ns t w(spch)m pulse duration, spiclk high (clock polarity = 1) 0.5t c(spc)m ? 10 0.5t c(spc)m 0.5 tc(spc)m + 0.5t c(lco) ? 10 0.5t c(spc)m + 0.5t c(lco) 6 t su(simo-spch)m setup time, spisimo data valid before spiclk high (clock polarity = 0) 0.5t c(spc)m ? 10 0.5t c(spc)m ? 10 ns t su(simo-spcl)m setup time, spisimo data valid before spiclk low (clock polarity = 1) 0.5t c(spc)m ? 10 0.5t c(spc)m ? 10 7 t v(spch-simo)m valid time, spisimo data valid after spiclk high (clock polarity = 0) 0.5t c(spc)m ? 10 0.5t c(spc)m ? 10 ns t v(spcl-simo)m valid time, spisimo data valid after spiclk low (clock polarity = 1) 0.5t c(spc)m ? 10 0.5t c(spc)m ? 10 10 t su(somi-spch)m setup time, spisomi before spiclk high (clock polarity = 0) 26 26 ns t su(somi-spcl)m setup time, spisomi before spiclk low (clock polarity = 1) 26 26 11 t v(spch-somi)m valid time, spisomi data valid after spiclk high (clock polarity = 0) 0.25t c(spc)m ? 10 0.5t c(spc)m ? 10 ns t v(spcl-somi)m valid time, spisomi data valid after spiclk low (clock polarity = 1) 0.25 tc(spc)m ? 10 0.5 tc(spc)m ? 10
103 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated a. in the master mode, spiste goes active 0.5t c(spc) (minimum) before valid spi clock edge. on the trailing end of the word, the spiste will go inactive 0.5t c(spc) after the receiving edge (spiclk) of the last data bit, except that spiste stays active between back-to-back transmit words in both fifo and non-fifo modes. figure 6-34. spi master mode external timing (clock phase = 1) data valid 11 spisomi spisimo spiclk (clock polarity = 1) spiclk (clock polarity = 0) master in data must be valid master out data is valid 1 7 6 10 3 2 spiste (a)
104 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) the master/slave bit (spictl.2) is cleared and the clock phase bit (spictl.3) is cleared. (2) t c(spc) = spi clock cycle time = lspclk/4 or lspclk/(spibrr + 1) (3) internal clock prescalers must be adjusted such that the spi clock speed is limited to the following spi clock rate: master mode transmit 20-mhz max, master mode receive 10-mhz max slave mode transmit 10-mhz max, slave mode receive 10-mhz max. (4) t c(lco) = lspclk cycle time (5) the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spiccr.6). 6.9.4.2 spi slave mode electrical data/timing table 6-37 lists the slave mode external timing (clock phase = 0) and table 6-38 lists the slave mode external timing (clock phase = 1). figure 6-35 and figure 6-36 show the timing waveforms. table 6-37. spi slave mode external timing (clock phase = 0) (1) (2) (3) (4) (5) no. min max unit 12 t c(spc)s cycle time, spiclk 4t c(lco) ns 13 t w(spch)s pulse duration, spiclk high (clock polarity = 0) 0.5t c(spc)s ? 10 0.5t c(spc)s ns t w(spcl)s pulse duration, spiclk low (clock polarity = 1) 0.5t c(spc)s ? 10 0.5t c(spc)s 14 t w(spcl)s pulse duration, spiclk low (clock polarity = 0) 0.5t c(spc)s ? 10 0.5t c(spc)s ns t w(spch)s pulse duration, spiclk high (clock polarity = 1) 0.5t c(spc)s ? 10 0.5t c(spc)s 15 t d(spch-somi)s delay time, spiclk high to spisomi valid (clock polarity = 0) 21 ns t d(spcl-somi)s delay time, spiclk low to spisomi valid (clock polarity = 1) 21 16 t v(spcl-somi)s valid time, spisomi data valid after spiclk low (clock polarity = 0) 0.75t c(spc)s ns t v(spch-somi)s valid time, spisomi data valid after spiclk high (clock polarity = 1) 0.75t c(spc)s 19 t su(simo-spcl)s setup time, spisimo before spiclk low (clock polarity = 0) 26 ns t su(simo-spch)s setup time, spisimo before spiclk high (clock polarity = 1) 26 20 t v(spcl-simo)s valid time, spisimo data valid after spiclk low (clock polarity = 0) 0.5t c(spc)s ? 10 ns t v(spch-simo)s valid time, spisimo data valid after spiclk high (clock polarity = 1) 0.5t c(spc)s ? 10 a. in the slave mode, the spiste signal should be asserted low at least 0.5t c(spc) (minimum) before the valid spi clock edge and remain low for at least 0.5t c(spc) after the receiving edge (spiclk) of the last data bit. figure 6-35. spi slave mode external timing (clock phase = 0) 20 15 spisimo spisomi spiclk (clock polarity = 1) spiclk (clock polarity = 0) spisimo data must be valid spisomi data is valid 19 16 14 13 12 spiste (a)
105 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) the master/slave bit (spictl.2) is cleared and the clock phase bit (spictl.3) is cleared. (2) t c(spc) = spi clock cycle time = lspclk/4 or lspclk/(spibrr + 1) (3) t c(lco) = lspclk cycle time (4) internal clock prescalers must be adjusted such that the spi clock speed is limited to the following spi clock rate: master mode transmit 20-mhz max, master mode receive 10-mhz max slave mode transmit 10-mhz max, slave mode receive 10-mhz max. (5) the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spiccr.6). table 6-38. spi slave mode external timing (clock phase = 1) (1) (2) (3) (4) (5) no. min max unit 12 t c(spc)s cycle time, spiclk 8t c(lco) ns 13 t w(spch)s pulse duration, spiclk high (clock polarity = 0) 0.5t c(spc)s ? 10 0.5t c(spc)s ns t w(spcl)s pulse duration, spiclk low (clock polarity = 1) 0.5t c(spc)s ? 10 0.5t c(spc)s 14 t w(spcl)s pulse duration, spiclk low (clock polarity = 0) 0.5t c(spc)s ? 10 0.5t c(spc)s ns t w(spch)s pulse duration, spiclk high (clock polarity = 1) 0.5t c(spc)s ? 10 0.5t c(spc)s 17 t su(somi-spch)s setup time, spisomi before spiclk high (clock polarity = 0) 0.125t c(spc)s ns t su(somi-spcl)s setup time, spisomi before spiclk low (clock polarity = 1) 0.125t c(spc)s 18 t v(spcl-somi)s valid time, spisomi data valid after spiclk low (clock polarity = 1) 0.75t c(spc)s ns t v(spch-somi)s valid time, spisomi data valid after spiclk high (clock polarity = 0) 0.75t c(spc)s 21 t su(simo-spch)s setup time, spisimo before spiclk high (clock polarity = 0) 26 ns t su(simo-spcl)s setup time, spisimo before spiclk low (clock polarity = 1) 26 22 t v(spch-simo)s valid time, spisimo data valid after spiclk high (clock polarity = 0) 0.5t c(spc)s ? 10 ns t v(spcl-simo)s valid time, spisimo data valid after spiclk low (clock polarity = 1) 0.5t c(spc)s ? 10 a. in the slave mode, the spiste signal should be asserted low at least 0.5t c(spc) before the valid spi clock edge and remain low for at least 0.5t c(spc) after the receiving edge (spiclk) of the last data bit. figure 6-36. spi slave mode external timing (clock phase = 1) data valid 22 spisimo spisomi spiclk (clock polarity = 1) spiclk (clock polarity = 0) spisimo data must be valid spisomi data is valid 21 12 18 17 14 13 spiste (a)
106 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.5 serial communications interface (sci) module the devices include two serial communications interface (sci) modules (sci-a, sci-b). the sci module supports digital communications between the cpu and other asynchronous peripherals that use the standard non-return-to-zero (nrz) format. the sci receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. both can be operated independently or simultaneously in the full-duplex mode. to ensure data integrity, the sci checks received data for break detection, parity, overrun, and framing errors. the bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register. features of each sci module include: ? two external pins: ? scitxd: sci transmit-output pin ? scirxd: sci receive-input pin note: both pins can be used as gpio if not used for sci. ? baud rate programmable to 64k different rates: ? data-word format ? one start bit ? data-word length programmable from 1 to 8 bits ? optional even/odd/no parity bit ? one or two stop bits ? four error-detection flags: parity, overrun, framing, and break detection ? two wake-up multiprocessor modes: idle-line and address bit ? half- or full-duplex operation ? double-buffered receive and transmit functions ? transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. ? transmitter: txrdy flag (transmitter-buffer register is ready to receive another character) and tx empty flag (transmitter-shift register is empty) ? receiver: rxrdy flag (receiver-buffer register is ready to receive another character), brkdt flag (break condition occurred), and rx error flag (monitoring four interrupt conditions) ? separate enable bits for transmitter and receiver interrupts (except brkdt) ? nrz (non-return-to-zero) format note all registers in this module are 8-bit registers that are connected to peripheral frame 2. when a register is accessed, the register data is in the lower byte (7 ? 0), and the upper byte (15 ? 8) is read as zeros. writing to the upper byte has no effect. enhanced features: ? auto baud-detect hardware logic ? 4-level transmit/receive fifo 8*1) (brr lspclk rate baud + = 0 brr when 1 16 lspclk rate baud = 0 brr when =
107 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) registers in this table are mapped to peripheral frame 2 space. this space only allows 16-bit accesses. 32-bit accesses produce undefined results. (2) these registers are new registers for the fifo mode. the sci port operation is configured and controlled by the registers listed in table 6-39 and table 6-40 . table 6-39. sci-a registers (1) name address size ( 16) eallow protected description sciccra 0x7050 1 no sci-a communications control register scictl1a 0x7051 1 no sci-a control register 1 scihbauda 0x7052 1 no sci-a baud register, high bits scilbauda 0x7053 1 no sci-a baud register, low bits scictl2a 0x7054 1 no sci-a control register 2 scirxsta 0x7055 1 no sci-a receive status register scirxemua 0x7056 1 no sci-a receive emulation data buffer register scirxbufa 0x7057 1 no sci-a receive data buffer register scitxbufa 0x7059 1 no sci-a transmit data buffer register scifftxa (2) 0x705a 1 no sci-a fifo transmit register sciffrxa (2) 0x705b 1 no sci-a fifo receive register sciffcta (2) 0x705c 1 no sci-a fifo control register scipria 0x705f 1 no sci-a priority control register (1) registers in this table are mapped to peripheral frame 2 space. this space only allows 16-bit accesses. 32-bit accesses produce undefined results. (2) these registers are new registers for the fifo mode. table 6-40. sci-b registers (1) name address size ( 16) description sciccrb 0x7750 1 sci-b communications control register scictl1b 0x7751 1 sci-b control register 1 scihbaudb 0x7752 1 sci-b baud register, high bits scilbaudb 0x7753 1 sci-b baud register, low bits scictl2b 0x7754 1 sci-b control register 2 scirxstb 0x7755 1 sci-b receive status register scirxemub 0x7756 1 sci-b receive emulation data buffer register scirxbufb 0x7757 1 sci-b receive data buffer register scitxbufb 0x7759 1 sci-b transmit data buffer register scifftxb (2) 0x775a 1 sci-b fifo transmit register sciffrxb (2) 0x775b 1 sci-b fifo receive register sciffctb (2) 0x775c 1 sci-b fifo control register sciprib 0x775f 1 sci-b priority control register
108 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated figure 6-37 shows the sci module block diagram. figure 6-37. serial communications interface (sci) module block diagram tx fifo _0 lspclk wut frame format and mode even/odd enable parity sci rx interrupt select logic brkdt rxrdy scirxst.6 scictl1.3 8 scictl2.1 rx/bk int ena scirxd scirxst.1 txena sci tx interrupt select logic tx empty txrdy scictl2.0 tx int ena scitxd rxena scirxd rxwake scictl1.6 rx err int ena txwake scitxd sciccr.6 sciccr.5 scitxbuf.7-0 scihbaud. 15 - 8 baud rate msbyte register scilbaud. 7 - 0 transmitter-data buffer register 8 scictl2.6 scictl2.7 baud rate lsbyte register rxshf register txshf register scirxst.5 1 tx fifo _1 ----- tx fifo _3 8 tx fifo registers tx fifo tx interrupt logic txint scifftx.14 rx fifo _3 scirxbuf.7-0 receive data buffer register scirxbuf.7-0 ----- rx fifo_1 rx fifo _0 8 rx fifo registers scictl1.0 rx interrupt logic rxint rx fifo sciffrx.15 rxffovf rx error scirxst.7 pe fe oe rx error scirxst.4 - 2 to cpu to cpu autobaud detect logic scictl1.1 sciffena interrupts interrupts
109 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.6 multichannel buffered serial port (mcbsp) module the mcbsp module has the following features: ? compatible to mcbsp in tms320c28x/tms320f28x dsp devices ? full-duplex communication ? double-buffered data registers that allow a continuous data stream ? independent framing and clocking for receive and transmit ? external shift clock generation or an internal programmable frequency shift clock ? a wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits ? 8-bit data transfers with lsb or msb first ? programmable polarity for both frame synchronization and data clocks ? highly programmable internal clock and frame generation ? direct interface to industry-standard codecs, analog interface chips (aics), and other serially connected analog-to-digital (a/d) and digital-to-analog (d/a) devices ? works with spi-compatible devices ? the following application interfaces can be supported on the mcbsp: ? t1/e1 framers ? iom-2 compliant devices ? ac97-compliant devices (the necessary multiphase frame synchronization capability is provided.) ? iis-compliant devices ? spi ? mcbsp clock rate, where clksrg source could be lspclk, clkx, or clkr. serial port performance is limited by i/o buffer switching speed. internal prescalers must be adjusted such that the peripheral speed is less than the i/o buffer speed limit. note see section 6.9 for maximum i/o pin toggling speed. note on the 80-pin package, only the clock-stop mode (spi) of the mcbsp is supported. ( ) clksrg clkg = 1 + clkgdv
110 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated figure 6-38 shows the block diagram of the mcbsp module. figure 6-38. mcbsp module 16 mcbsp receive interrupt select logic mdxx mdrx expand logic drr1 receive buffer rx interrupt drr2 receive buffer rbr1 register rbr2 register mclkxx mfsxx mclkrx mfsrx 16 compand logic dxr2 transmit buffer rsr1 xsr2 xsr1 peripheral read bus 16 16 16 16 16 rsr2 dxr1 transmit buffer lspclk mrint to cpu rx interrupt logic mcbsp transmit interrupt select logic tx interrupt mxint to cpu tx interrupt logic 16 16 16 bridge dma bus peripheral bus peripheral write bus cpu cpu cpu
111 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated table 6-41 provides a summary of the mcbsp registers. table 6-41. mcbsp register summary name mcbsp-a address type reset value description data registers, receive, transmit drr2 0x5000 r 0x0000 mcbsp data receive register 2 drr1 0x5001 r 0x0000 mcbsp data receive register 1 dxr2 0x5002 w 0x0000 mcbsp data transmit register 2 dxr1 0x5003 w 0x0000 mcbsp data transmit register 1 mcbsp control registers spcr2 0x5004 r/w 0x0000 mcbsp serial port control register 2 spcr1 0x5005 r/w 0x0000 mcbsp serial port control register 1 rcr2 0x5006 r/w 0x0000 mcbsp receive control register 2 rcr1 0x5007 r/w 0x0000 mcbsp receive control register 1 xcr2 0x5008 r/w 0x0000 mcbsp transmit control register 2 xcr1 0x5009 r/w 0x0000 mcbsp transmit control register 1 srgr2 0x500a r/w 0x0000 mcbsp sample rate generator register 2 srgr1 0x500b r/w 0x0000 mcbsp sample rate generator register 1 multichannel control registers mcr2 0x500c r/w 0x0000 mcbsp multichannel register 2 mcr1 0x500d r/w 0x0000 mcbsp multichannel register 1 rcera 0x500e r/w 0x0000 mcbsp receive channel enable register partition a rcerb 0x500f r/w 0x0000 mcbsp receive channel enable register partition b xcera 0x5010 r/w 0x0000 mcbsp transmit channel enable register partition a xcerb 0x5011 r/w 0x0000 mcbsp transmit channel enable register partition b pcr 0x5012 r/w 0x0000 mcbsp pin control register rcerc 0x5013 r/w 0x0000 mcbsp receive channel enable register partition c rcerd 0x5014 r/w 0x0000 mcbsp receive channel enable register partition d xcerc 0x5015 r/w 0x0000 mcbsp transmit channel enable register partition c xcerd 0x5016 r/w 0x0000 mcbsp transmit channel enable register partition d rcere 0x5017 r/w 0x0000 mcbsp receive channel enable register partition e rcerf 0x5018 r/w 0x0000 mcbsp receive channel enable register partition f xcere 0x5019 r/w 0x0000 mcbsp transmit channel enable register partition e xcerf 0x501a r/w 0x0000 mcbsp transmit channel enable register partition f rcerg 0x501b r/w 0x0000 mcbsp receive channel enable register partition g rcerh 0x501c r/w 0x0000 mcbsp receive channel enable register partition h xcerg 0x501d r/w 0x0000 mcbsp transmit channel enable register partition g xcerh 0x501e r/w 0x0000 mcbsp transmit channel enable register partition h mffint 0x5023 r/w 0x0000 mcbsp interrupt enable register
112 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.6.1 mcbsp electrical data/timing 6.9.6.1.1 mcbsp transmit and receive timing (1) polarity bits clkrp = clkxp = fsrp = fsxp = 0. if the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) 2p = 1/clkg in ns. clkg is the output of sample rate generator mux. clkg = clksrg/(1 + clkgdv). clksrg can be lspclk, clkx, clkr as source. clksrg (sysclkout/2). mcbsp performance is limited by i/o buffer switching speed. (3) internal clock prescalers must be adjusted such that the mcbsp clock (clkg, clkx, clkr) speeds are not greater than the i/o buffer speed limit (20 mhz). (4) maximum mcbsp module clock frequency decreases to 10 mhz for internal clkr. table 6-42. mcbsp timing requirements (1) (2) no. min max unit mcbsp module clock (clkg, clkx, clkr) range 1 khz 20 (3) (4) mhz mcbsp module cycle time (clkg, clkx, clkr) range 50 (4) ns 1 ms m11 t c(ckrx) cycle time, clkr/x clkr/x ext 2p ns m12 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x ext p ? 7 ns m13 t r(ckrx) rise time, clkr/x clkr/x ext 7 ns m14 t f(ckrx) fall time, clkr/x clkr/x ext 7 ns m15 t su(frh-ckrl) setup time, external fsr high before clkr low clkr int 18 ns clkr ext 2 m16 t h(ckrl-frh) hold time, external fsr high after clkr low clkr int 0 ns clkr ext 6 m17 t su(drv-ckrl) setup time, dr valid before clkr low clkr int 18 ns clkr ext 2 m18 t h(ckrl-drv) hold time, dr valid after clkr low clkr int 0 ns clkr ext 6 m19 t su(fxh-ckxl) setup time, external fsx high before clkx low clkx int 18 ns clkx ext 2 m20 t h(ckxl-fxh) hold time, external fsx high after clkx low clkx int 0 ns clkx ext 6
113 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) polarity bits clkrp = clkxp = fsrp = fsxp = 0. if the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) 2p = 1/clkg in ns. (3) c = clkrx low pulse width = p d = clkrx high pulse width = p table 6-43. mcbsp switching characteristics (1) (2) over recommended operating conditions (unless otherwise noted) no. parameter min max unit m1 t c(ckrx) cycle time, clkr/x clkr/x int 2p ns m2 t w(ckrxh) pulse duration, clkr/x high clkr/x int d ? 5 (3) d + 5 (3) ns m3 t w(ckrxl) pulse duration, clkr/x low clkr/x int c ? 5 (3) c + 5 (3) ns m4 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr int 0 4 ns clkr ext 3 27 m5 t d(ckxh-fxv) delay time, clkx high to internal fsx valid clkx int 0 4 ns clkx ext 3 27 m6 t dis(ckxh-dxhz) disable time, clkx high to dx high impedance following last data bit clkx int 8 ns clkx ext 14 m7 t d(ckxh-dxv) delay time, clkx high to dx valid. clkx int 9 ns this applies to all bits except the first bit transmitted. clkx ext 28 delay time, clkx high to dx valid dxena = 0 clkx int 8 clkx ext 14 only applies to first bit transmitted when in data delay 1 or 2 (xdatdly=01b or 10b) modes dxena = 1 clkx int p + 8 clkx ext p + 14 m8 t en(ckxh-dx) enable time, clkx high to dx driven dxena = 0 clkx int 0 ns clkx ext 6 only applies to first bit transmitted when in data delay 1 or 2 (xdatdly=01b or 10b) modes dxena = 1 clkx int p clkx ext p + 6 m9 t d(fxh-dxv) delay time, fsx high to dx valid dxena = 0 fsx int 8 ns fsx ext 14 only applies to first bit transmitted when in data delay 0 (xdatdly=00b) mode. dxena = 1 fsx int p + 8 fsx ext p + 14 m10 t en(fxh-dx) enable time, fsx high to dx driven dxena = 0 fsx int 0 ns fsx ext 6 only applies to first bit transmitted when in data delay 0 (xdatdly=00b) mode dxena = 1 fsx int p fsx ext p + 6
114 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated figure 6-39. mcbsp receive timing figure 6-40. mcbsp transmit timing m8 m7 m7 m8 m6 m7 m9 m10 (xdatdly=10b) dx (xdatdly=01b) dx (xdatdly=00b) dx (n?2) bit (n?1) bit 0 (n?4) bit (n?1) (n?3) (n?2) bit 0 (n?3) (n?2) bit (n?1) bit 0 m20 m14 m13 m3, m12 m1, m1 1 m2, m12 fsx (ext) fsx (int) clkx m5 m5 m19 (n?2) bit (n?1) (n?3) (n?2) bit (n?1) (n?4) (n?3) (n?2) bit (n?1) m18 m17 m18 m17 m17 m18 m16 m15 m4 m4 m14 m13 m3, m12 m1, m1 1 m2, m12 (rdatdly=10b) dr (rdatdly=01b) dr (rdatdly=00b) dr fsr (ext) fsr (int) clkr
115 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.6.1.2 mcbsp as spi master or slave timing (1) for all spi slave modes, clkx has to be a minimum of 8 clkg cycles. furthermore, clkg should be lspclk/2 by setting clksm = clkgdv = 1. (2) 2p = 1/clkg table 6-44. mcbsp as spi master or slave timing requirements (clkstp = 10b, clkxp = 0) (1) no. master slave unit min max min max m30 t su(drv-ckxl) setup time, dr valid before clkx low 30 8p ? 10 ns m31 t h(ckxl-drv) hold time, dr valid after clkx low 1 8p ? 10 ns m32 t su(bfxl-ckxh) setup time, fsx low before clkx high 8p + 10 ns m33 t c(ckx) cycle time, clkx 2p (2) 16p ns (1) 2p = 1/clkg table 6-45. mcbsp as spi master or slave switching characteristics (clkstp = 10b, clkxp = 0) over recommended operating conditions (unless otherwise noted) no. parameter master slave unit min max min max m24 t h(ckxl-fxl) hold time, fsx low after clkx low 2p (1) ns m25 t d(fxl-ckxh) delay time, fsx low to clkx high p ns m26 t d(ckxh-dxv) delay time, clkx high to dx valid ? 2 0 3p + 6 5p + 20 ns m28 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high 6 6p + 6 ns m29 t d(fxl-dxv) delay time, fsx low to dx valid 6 4p + 6 ns figure 6-41. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 0 bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) clkx fsx dx m30 m31 dr m28 m24 m29 lsb msb m32 m33 m25 m26
116 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) for all spi slave modes, clkx has to be a minimum of 8 clkg cycles. furthermore, clkg should be lspclk/2 by setting clksm = clkgdv = 1. (2) 2p = 1/clkg table 6-46. mcbsp as spi master or slave timing requirements (clkstp = 11b, clkxp = 0) (1) no. master slave unit min max min max m39 t su(drv-ckxh) setup time, dr valid before clkx high 30 8p ? 10 ns m40 t h(ckxh-drv) hold time, dr valid after clkx high 1 8p ? 10 ns m41 t su(fxl-ckxh) setup time, fsx low before clkx high 16p + 10 ns m42 t c(ckx) cycle time, clkx 2p (2) 16p ns (1) 2p = 1/clkg table 6-47. mcbsp as spi master or slave switching characteristics (clkstp = 11b, clkxp = 0) over recommended operating conditions (unless otherwise noted) no. parameter master slave unit min max min max m34 t h(ckxl-fxl) hold time, fsx low after clkx low p ns m35 t d(fxl-ckxh) delay time, fsx low to clkx high 2p (1) ns m36 t d(ckxl-dxv) delay time, clkx low to dx valid ? 2 0 3p + 6 5p + 20 ns m37 t dis(ckxl-dxhz) disable time, dx high impedance following last data bit from clkx low p + 6 7p + 6 ns m38 t d(fxl-dxv) delay time, fsx low to dx valid 6 4p + 6 ns figure 6-42. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 0 bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) clkx fsx dx dr m35 m37 m40 m39 m38 lsb msb m41 m42 m34 m36
117 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) for all spi slave modes, clkx has to be a minimum of 8 clkg cycles. furthermore, clkg should be lspclk/2 by setting clksm = clkgdv = 1. (2) 2p = 1/clkg table 6-48. mcbsp as spi master or slave timing requirements (clkstp = 10b, clkxp = 1) (1) no. master slave unit min max min max m49 t su(drv-ckxh) setup time, dr valid before clkx high 30 8p ? 10 ns m50 t h(ckxh-drv) hold time, dr valid after clkx high 1 8p ? 10 ns m51 t su(fxl-ckxl) setup time, fsx low before clkx low 8p + 10 ns m52 t c(ckx) cycle time, clkx 2p (2) 16p ns (1) 2p = 1/clkg table 6-49. mcbsp as spi master or slave switching characteristics (clkstp = 10b, clkxp = 1) over recommended operating conditions (unless otherwise noted) no. parameter master slave unit min max min max m43 t h(ckxh-fxl) hold time, fsx low after clkx high 2p (1) ns m44 t d(fxl-ckxl) delay time, fsx low to clkx low p ns m45 t d(ckxl-dxv) delay time, clkx low to dx valid ? 2 0 3p + 6 5p + 20 ns m47 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high 6 6p + 6 ns m48 t d(fxl-dxv) delay time, fsx low to dx valid 6 4p + 6 ns figure 6-43. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 1 m51 m50 m47 bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) clkx fsx dx dr m48 m49 m43 lsb msb m52 m44 m45
118 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) for all spi slave modes, clkx has to be a minimum of 8 clkg cycles. furthermore, clkg should be lspclk/2 by setting clksm = clkgdv = 1. (2) 2p = 1/clkg table 6-50. mcbsp as spi master or slave timing requirements (clkstp = 11b, clkxp = 1) (1) no. master slave unit min max min max m58 t su(drv-ckxl) setup time, dr valid before clkx low 30 8p ? 10 ns m59 t h(ckxl-drv) hold time, dr valid after clkx low 1 8p ? 10 ns m60 t su(fxl-ckxl) setup time, fsx low before clkx low 16p + 10 ns m61 t c(ckx) cycle time, clkx 2p (2) 16p ns (1) 2p = 1/clkg table 6-51. mcbsp as spi master or slave switching characteristics (clkstp = 11b, clkxp = 1) (1) over recommended operating conditions (unless otherwise noted) no. parameter master slave unit min max min max m53 t h(ckxh-fxl) hold time, fsx low after clkx high p ns m54 t d(fxl-ckxl) delay time, fsx low to clkx low 2p (1) ns m55 t d(ckxh-dxv) delay time, clkx high to dx valid ? 2 0 3p + 6 5p + 20 ns m56 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high p + 6 7p + 6 ns m57 t d(fxl-dxv) delay time, fsx low to dx valid 6 4p + 6 ns figure 6-44. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 1 bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) clkx fsx dx dr m54 m58 m56 m53 m55 m59 m57 lsb msb m60 m61
119 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.7 enhanced controller area network (ecan) module the can module (ecan-a) has the following features: ? fully compliant with can protocol, version 2.0b ? supports data rates up to 1 mbps ? thirty-two mailboxes, each with the following properties: ? configurable as receive or transmit ? configurable with standard or extended identifier ? has a programmable receive mask ? supports data and remote frame ? composed of 0 to 8 bytes of data ? uses a 32-bit time stamp on receive and transmit message ? protects against reception of new message ? holds the dynamically programmable priority of transmit message ? employs a programmable interrupt scheme with two interrupt levels ? employs a programmable alarm on transmission or reception time-out ? low-power mode ? programmable wake-up on bus activity ? automatic reply to a remote request message ? automatic retransmission of a frame in case of loss of arbitration or error ? 32-bit local network time counter synchronized by a specific message (communication in conjunction with mailbox 16) ? self-test mode ? operates in a loopback mode receiving its own message. a "dummy" acknowledge is provided, thereby eliminating the need for another node to provide the acknowledge bit. note for a sysclkout of 90 mhz, the smallest bit rate possible is 6.25 kbps. the f2806x can has passed the conformance test per iso/dis 16845. contact ti for test report and exceptions.
120 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated figure 6-45. ecan block diagram and interface circuit table 6-52. 3.3-v ecan transceivers part number supply voltage low-power mode slope control vref other t a sn65hvd230 3.3 v standby adjustable yes ? ? 40 c to 85 c sn65hvd230q 3.3 v standby adjustable yes ? ? 40 c to 125 c sn65hvd231 3.3 v sleep adjustable yes ? ? 40 c to 85 c sn65hvd231q 3.3 v sleep adjustable yes ? ? 40 c to 125 c sn65hvd232 3.3 v none none none ? ? 40 c to 85 c sn65hvd232q 3.3 v none none none ? ? 40 c to 125 c sn65hvd233 3.3 v standby adjustable none diagnostic loopback ? 40 c to 125 c sn65hvd234 3.3 v standby and sleep adjustable none ? ? 40 c to 125 c sn65hvd235 3.3 v standby adjustable none autobaud loopback ? 40 c to 125 c iso1050 3 ? 5.5 v none none none built-in isolation low prop delay thermal shutdown fail-safe operation dominant time-out ? 55 c to 105 c mailbox ram (512 bytes) 32-message mailbox of 4 32-bit words memory management unit cpu interface, receive control unit, timer management unit ecan memory (512 bytes) registers and message objects control message controller 32 32 ecan protocol kernel receive buffer transmit buffer control buffer status buffer enhanced can controller 32 controls address data ecan1int ecan0int 32 sn65hvd23x 3.3-v can transceiver can bus
121 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated figure 6-46. ecan-a memory map note if the ecan module is not used in an application, the ram available (lam, mots, moto, and mailbox ram) can be used as general-purpose ram. the can module clock should be enabled for this. mailbox enable - canme mailbox direction - canmd transmission request set - cantrs transmission request reset - cantrr transmission acknowledge - canta abort acknowledge - canaa received message pending - canrmp received message lost - canrml remote frame pending - canrfp global acceptance mask - cangam master control - canmc bit-timing configuration - canbtc error and status - canes transmit error counter - cantec receive error counter - canrec global interrupt flag 0 - cangif0 global interrupt mask - cangim mailbox interrupt mask - canmim mailbox interrupt level - canmil overwrite protection control - canopc tx i/o control - cantioc rx i/o control - canrioc time stamp counter - cantsc global interrupt flag 1 - cangif1 time-out control - cantoc time-out status - cantos reserved ecan-a control and status registers message identifier - msgid 61e8h-61e9h message control - msgctrl message data low - mdl message data high - mdh message mailbox (16 bytes) control and status registers 6000h 603fh local acceptance masks (lam) (32 32-bit ram) 6040h 607fh 6080h 60bfh 60c0h 60ffh ecan-a memory (512 bytes) message object time stamps (mots) (32 32-bit ram) message object time-out (moto) (32 32-bit ram) mailbox 0 6100h-6107h mailbox 1 6108h-610fh mailbox 2 6110h-6117h mailbox 3 6118h-611fh ecan-a memory ram (512 bytes) mailbox 4 6120h-6127h mailbox 28 61e0h-61e7h mailbox 29 61e8h-61efh mailbox 30 61f0h-61f7h mailbox 31 61f8h-61ffh 61eah-61ebh 61ech-61edh 61eeh-61efh
122 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) these registers are mapped to peripheral frame 1. the can registers listed in table 6-53 are used by the cpu to configure and control the can controller and the message objects. ecan control registers only support 32-bit read/write operations. mailbox ram can be accessed as 16 bits or 32 bits. all 32-bit accesses are aligned to an even boundary. table 6-53. can registers (1) register name ecan-a address size ( 32) description canme 0x6000 1 mailbox enable canmd 0x6002 1 mailbox direction cantrs 0x6004 1 transmit request set cantrr 0x6006 1 transmit request reset canta 0x6008 1 transmission acknowledge canaa 0x600a 1 abort acknowledge canrmp 0x600c 1 receive message pending canrml 0x600e 1 receive message lost canrfp 0x6010 1 remote frame pending cangam 0x6012 1 global acceptance mask canmc 0x6014 1 master control canbtc 0x6016 1 bit-timing configuration canes 0x6018 1 error and status cantec 0x601a 1 transmit error counter canrec 0x601c 1 receive error counter cangif0 0x601e 1 global interrupt flag 0 cangim 0x6020 1 global interrupt mask cangif1 0x6022 1 global interrupt flag 1 canmim 0x6024 1 mailbox interrupt mask canmil 0x6026 1 mailbox interrupt level canopc 0x6028 1 overwrite protection control cantioc 0x602a 1 tx i/o control canrioc 0x602c 1 rx i/o control cantsc 0x602e 1 time stamp counter (reserved in scc mode) cantoc 0x6030 1 time-out control (reserved in scc mode) cantos 0x6032 1 time-out status (reserved in scc mode)
123 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.8 inter-integrated circuit (i 2 c) the device contains one i 2 c serial port. figure 6-47 shows how the i 2 c peripheral module interfaces within the device. the i 2 c module has the following features: ? compliance with the philips semiconductors i 2 c-bus specification (version 2.1): ? support for 1-bit to 8-bit format transfers ? 7-bit and 10-bit addressing modes ? general call ? start byte mode ? support for multiple master-transmitters and slave-receivers ? support for multiple slave-transmitters and master-receivers ? combined master transmit/receive and receive/transmit mode ? data transfer rate of from 10 kbps up to 400 kbps (i 2 c fast-mode rate) ? one 4-word receive fifo and one 4-word transmit fifo ? one interrupt that can be used by the cpu. this interrupt can be generated as a result of one of the following conditions: ? transmit-data ready ? receive-data ready ? register-access ready ? no-acknowledgment received ? arbitration lost ? stop condition detected ? addressed as slave ? an additional interrupt that can be used by the cpu when in fifo mode ? module enable/disable capability ? free data format mode
124 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated a. the i 2 c registers are accessed at the sysclkout rate. the internal timing and signal waveforms of the i 2 c port are also at the sysclkout rate. b. the clock enable bit (i2caenclk) in the pclkcro register turns off the clock to the i 2 c port for low power operation. upon reset, i2caenclk is clear, which indicates the peripheral internal clocks are off. figure 6-47. i 2 c peripheral module interfaces the registers in table 6-54 configure and control the i 2 c port operation. table 6-54. i2c-a registers name address eallow protected description i2coar 0x7900 no i 2 c own address register i2cier 0x7901 no i 2 c interrupt enable register i2cstr 0x7902 no i 2 c status register i2cclkl 0x7903 no i 2 c clock low-time divider register i2cclkh 0x7904 no i 2 c clock high-time divider register i2ccnt 0x7905 no i 2 c data count register i2cdrr 0x7906 no i 2 c data receive register i2csar 0x7907 no i 2 c slave address register i2cdxr 0x7908 no i 2 c data transmit register i2cmdr 0x7909 no i 2 c mode register i2cisrc 0x790a no i 2 c interrupt source register i2cpsc 0x790c no i 2 c prescaler register i2cfftx 0x7920 no i 2 c fifo transmit register i2cffrx 0x7921 no i 2 c fifo receive register i2crsr ? no i 2 c receive shift register (not accessible to the cpu) i2cxsr ? no i 2 c transmit shift register (not accessible to the cpu) i2cxsr i2cdxr i2crsr i2cdrr clock synchronizer prescaler noise filters arbitrator i2c int peripheral bus interrupt to cpu/pie sda scl control/status registers cpu i c module 2 tx fifo rx fifo fifo interrupt to cpu/pie
125 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.8.1 i 2 c electrical data/timing table 6-55. i 2 c timing test conditions min max unit f scl scl clock frequency i 2 c clock module frequency is between 7 mhz and 12 mhz and i 2 c prescaler and clock divider registers are configured appropriately 400 khz v il low level input voltage 0.3 v ddio v v ih high level input voltage 0.7 v ddio v v hys input hysteresis 0.05 v ddio v v ol low level output voltage 3-ma sink current 0 0.4 v t low low period of scl clock i 2 c clock module frequency is between 7 mhz and 12 mhz and i 2 c prescaler and clock divider registers are configured appropriately 1.3 s t high high period of scl clock i 2 c clock module frequency is between 7 mhz and 12 mhz and i 2 c prescaler and clock divider registers are configured appropriately 0.6 s l i input current with an input voltage between 0.1 v ddio and 0.9 v ddio max ? 10 10 a
126 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.9 enhanced pulse width modulator (epwm) modules (epwm1 ? epwm8) the devices contain up to eight enhanced pwm (epwm) modules. figure 6-48 shows a block diagram of multiple epwm modules. figure 6-49 shows the signal interconnections with the epwm. table 6-56 and table 6-57 show the complete epwm register set per module. a. this signal exists only on devices with an eqep1 module. figure 6-48. epwm epwm1tzint pie epwm1int epwm2tzint epwm2int epwmxtzint epwmxint compout1compout2 comp soca1 adc socb1 soca2 socb2 socax socbx epwm1synci epwm2synci epwm1syncoepwm2synco epwm1 module epwm2 module epwmxsynci epwmx module tz6 tz6 tz1 tz3 to tz5 clockfail tz4 eqep1err (a) emustop tz5 clockfail tz4 eqep1err (a) emustop epwm1enclk tbclksync epwm2enclk tbclksync tz5 tz6 epwmxenclk tbclksync clockfail tz4 eqep1err (a) emustop epwm1b c28x cpu system control eqep1 tz1 tz3 to tz1 tz3 to epwm1synco epwm2b ecapi epwmxb eqep1err hr p w m epwmxa epwm2a epwm1a g p i o m u x adcsocbo adcsocao peripheral bus pulse stretch (32 sysclkout cycles, active-low output) soca1soca2 spcax pulse stretch (32 sysclkout cycles, active-low output) socb1socb2 spcbx epwmsynci
copyright ? 2010 ? 2016, texas instruments incorporated detailed description submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 127 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 (1) registers that are eallow protected. table 6-56. epwm1 ? epwm4 control and status registers name epwm1 epwm2 epwm3 epwm4 size ( 16)/ #shadow description tbctl 0x6800 0x6840 0x6880 0x68c0 1/0 time base control register tbsts 0x6801 0x6841 0x6881 0x68c1 1/0 time base status register tbphshr 0x6802 0x6842 0x6882 0x68c2 1/0 time base phase hrpwm register tbphs 0x6803 0x6843 0x6883 0x68c3 1/0 time base phase register tbctr 0x6804 0x6844 0x6884 0x68c4 1/0 time base counter register tbprd 0x6805 0x6845 0x6885 0x68c5 1/1 time base period register set tbprdhr 0x6806 0x6846 0x6886 0x68c6 1/1 time base period high-resolution register (1) cmpctl 0x6807 0x6847 0x6887 0x68c7 1/0 counter compare control register cmpahr 0x6808 0x6848 0x6888 0x68c8 1/1 time base compare a hrpwm register cmpa 0x6809 0x6849 0x6889 0x68c9 1/1 counter compare a register set cmpb 0x680a 0x684a 0x688a 0x68ca 1/1 counter compare b register set aqctla 0x680b 0x684b 0x688b 0x68cb 1/0 action qualifier control register for output a aqctlb 0x680c 0x684c 0x688c 0x68cc 1/0 action qualifier control register for output b aqsfrc 0x680d 0x684d 0x688d 0x68cd 1/0 action qualifier software force register aqcsfrc 0x680e 0x684e 0x688e 0x68ce 1/1 action qualifier continuous s/w force register set dbctl 0x680f 0x684f 0x688f 0x68cf 1/1 dead-band generator control register dbred 0x6810 0x6850 0x6890 0x68d0 1/0 dead-band generator rising edge delay count register dbfed 0x6811 0x6851 0x6891 0x68d1 1/0 dead-band generator falling edge delay count register tzsel 0x6812 0x6852 0x6892 0x68d2 1/0 trip zone select register (1) tzdcsel 0x6813 0x6853 0x6893 0x68d3 1/0 trip zone digital compare register tzctl 0x6814 0x6854 0x6894 0x68d4 1/0 trip zone control register (1) tzeint 0x6815 0x6855 0x6895 0x68d5 1/0 trip zone enable interrupt register (1) tzflg 0x6816 0x6856 0x6896 0x68d6 1/0 trip zone flag register (1) tzclr 0x6817 0x6857 0x6897 0x68d7 1/0 trip zone clear register (1) tzfrc 0x6818 0x6858 0x6898 0x68d8 1/0 trip zone force register (1) etsel 0x6819 0x6859 0x6899 0x68d9 1/0 event trigger selection register etps 0x681a 0x685a 0x689a 0x68da 1/0 event trigger prescale register etflg 0x681b 0x685b 0x689b 0x68db 1/0 event trigger flag register etclr 0x681c 0x685c 0x689c 0x68dc 1/0 event trigger clear register etfrc 0x681d 0x685d 0x689d 0x68dd 1/0 event trigger force register pcctl 0x681e 0x685e 0x689e 0x68de 1/0 pwm chopper control register hrcnfg 0x6820 0x6860 0x68a0 0x68e0 1/0 hrpwm configuration register (1)
copyright ? 2010 ? 2016, texas instruments incorporated detailed description submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 128 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com table 6-56. epwm1 ? epwm4 control and status registers (continued) name epwm1 epwm2 epwm3 epwm4 size ( 16)/ #shadow description (2) w = write to shadow register hrmstep 0x6826 - - - 1/0 hrpwm mep step register hrpctl 0x6828 0x6868 0x68a8 0x68e8 1/0 high-resolution period control register (1) tbprdhrm 0x682a 0x686a 0x68aa 0x68ea 1/w (2) time base period hrpwm register mirror tbprdm 0x682b 0x686b 0x68ab 0x68eb 1/w (2) time base period register mirror cmpahrm 0x682c 0x686c 0x68ac 0x68ec 1/w (2) compare a hrpwm register mirror cmpam 0x682d 0x686d 0x68ad 0x68ed 1/w (2) compare a register mirror dctripsel 0x6830 0x6870 0x68b0 0x68f0 1/0 digital compare trip select register (1) dcactl 0x6831 0x6871 0x68b1 0x68f1 1/0 digital compare a control register (1) dcbctl 0x6832 0x6872 0x68b2 0x68f2 1/0 digital compare b control register (1) dcfctl 0x6833 0x6873 0x68b3 0x68f3 1/0 digital compare filter control register (1) dccapct 0x6834 0x6874 0x68b4 0x68f4 1/0 digital compare capture control register (1) dcfoffset 0x6835 0x6875 0x68b5 0x68f5 1/1 digital compare filter offset register dcfoffsetcnt 0x6836 0x6876 0x68b6 0x68f6 1/0 digital compare filter offset counter register dcfwindow 0x6837 0x6877 0x68b7 0x68f7 1/0 digital compare filter window register dcfwindowcnt 0x6838 0x6878 0x68b8 0x68f8 1/0 digital compare filter window counter register dccap 0x6839 0x6879 0x68b9 0x68f9 1/1 digital compare counter capture register (1) registers that are eallow protected. table 6-57. epwm5 ? epwm8 control and status registers name epwm5 epwm6 epwm7 epwm8 size ( 16)/ #shadow description tbctl 0x6900 0x6940 0x6980 0x69c0 1/0 time base control register tbsts 0x6901 0x6941 0x6981 0x69c1 1/0 time base status register tbphshr 0x6902 0x6942 0x6982 0x69c2 1/0 time base phase hrpwm register tbphs 0x6903 0x6943 0x6983 0x69c3 1/0 time base phase register tbctr 0x6904 0x6944 0x6984 0x69c4 1/0 time base counter register tbprd 0x6905 0x6945 0x6985 0x69c5 1/1 time base period register set tbprdhr 0x6906 0x6946 0x6986 0x69c6 1/1 time base period high-resolution register (1) cmpctl 0x6907 0x6947 0x6987 0x69c7 1/0 counter compare control register cmpahr 0x6908 0x6948 0x6988 0x69c8 1/1 time base compare a hrpwm register cmpa 0x6909 0x6949 0x6989 0x69c9 1/1 counter compare a register set cmpb 0x690a 0x694a 0x698a 0x69ca 1/1 counter compare b register set
copyright ? 2010 ? 2016, texas instruments incorporated detailed description submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 129 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 table 6-57. epwm5 ? epwm8 control and status registers (continued) name epwm5 epwm6 epwm7 epwm8 size ( 16)/ #shadow description (2) w = write to shadow register aqctla 0x690b 0x694b 0x698b 0x69cb 1/0 action qualifier control register for output a aqctlb 0x690c 0x694c 0x698c 0x69cc 1/0 action qualifier control register for output b aqsfrc 0x690d 0x694d 0x698d 0x69cd 1/0 action qualifier software force register aqcsfrc 0x690e 0x694e 0x698e 0x69ce 1/1 action qualifier continuous s/w force register set dbctl 0x690f 0x694f 0x698f 0x69cf 1/1 dead-band generator control register dbred 0x6910 0x6950 0x6990 0x69d0 1/0 dead-band generator rising edge delay count register dbfed 0x6911 0x6951 0x6991 0x69d1 1/0 dead-band generator falling edge delay count register tzsel 0x6912 0x6952 0x6992 0x69d2 1/0 trip zone select register (1) tzdcsel 0x6913 0x6953 0x6993 0x69d3 1/0 trip zone digital compare register tzctl 0x6914 0x6954 0x6994 0x69d4 1/0 trip zone control register (1) tzeint 0x6915 0x6955 0x6995 0x69d5 1/0 trip zone enable interrupt register (1) tzflg 0x6916 0x6956 0x6996 0x69d6 1/0 trip zone flag register (1) tzclr 0x6917 0x6957 0x6997 0x69d7 1/0 trip zone clear register (1) tzfrc 0x6918 0x6958 0x6998 0x69d8 1/0 trip zone force register (1) etsel 0x6919 0x6959 0x6999 0x69d9 1/0 event trigger selection register etps 0x691a 0x695a 0x699a 0x69da 1/0 event trigger prescale register etflg 0x691b 0x695b 0x699b 0x69db 1/0 event trigger flag register etclr 0x691c 0x695c 0x699c 0x69dc 1/0 event trigger clear register etfrc 0x691d 0x695d 0x699d 0x69dd 1/0 event trigger force register pcctl 0x691e 0x695e 0x699e 0x69de 1/0 pwm chopper control register hrcnfg 0x6920 0x6960 0x69a0 0x69e0 1/0 hrpwm configuration register (1) hrmstep - - - - 1/0 hrpwm mep step register hrpctl 0x6928 0x6968 0x69a8 0x69e8 1/0 high-resolution period control register (1) tbprdhrm 0x692a 0x696a 0x69aa 0x69ea 1/w (2) time base period hrpwm register mirror tbprdm 0x692b 0x696b 0x69ab 0x69eb 1/w (2) time base period register mirror cmpahrm 0x692c 0x696c 0x69ac 0x69ec 1/w (2) compare a hrpwm register mirror cmpam 0x692d 0x696d 0x69ad 0x69ed 1/w (2) compare a register mirror dctripsel 0x6930 0x6970 0x69b0 0x69f0 1/0 digital compare trip select register (1) dcactl 0x6931 0x6971 0x69b1 0x69f1 1/0 digital compare a control register (1) dcbctl 0x6932 0x6972 0x69b2 0x69f2 1/0 digital compare b control register (1) dcfctl 0x6933 0x6973 0x69b3 0x69f3 1/0 digital compare filter control register (1) dccapct 0x6934 0x6974 0x69b4 0x69f4 1/0 digital compare capture control register (1)
copyright ? 2010 ? 2016, texas instruments incorporated detailed description submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 130 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com table 6-57. epwm5 ? epwm8 control and status registers (continued) name epwm5 epwm6 epwm7 epwm8 size ( 16)/ #shadow description dcfoffset 0x6935 0x6975 0x69b5 0x69f5 1/1 digital compare filter offset register dcfoffsetcnt 0x6936 0x6976 0x69b6 0x69f6 1/0 digital compare filter offset counter register dcfwindow 0x6937 0x6977 0x69b7 0x69f7 1/0 digital compare filter window register dcfwindowcnt 0x6938 0x6978 0x69b8 0x69f8 1/0 digital compare filter window counter register dccap 0x6939 0x6979 0x69b9 0x69f9 1/1 digital compare counter capture register
131 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated a. these events are generated by the type 1 epwm digital compare (dc) submodule based on the levels of the compxout and tz signals. b. this signal exists only on devices with an eqep1 module. figure 6-49. epwm submodules showing critical internal signal interconnections tbprd shadow (24) tbprd active (24) counter up/down (16 bit) tcbnt active (16) tbctl[phsen] ctr=prd 16 phasecontrol 8 ctr=zero ctr_dir tbphshr (8) tbprdhr (8) 8 ctr=zero ctr=cmpb disabled tbctl[syncosel] epwmxsynco time-base (tb) tbphs active (24) sync in/out select mux ctr=prd ctr=zero ctr=cmpa ctr=cmpb ctr_dir dcaevt1.soc (a) dcbevt1.soc (a) event trigger and interrupt (et) epwmxint epwmxsoca epwmxsocb epwmxsoca epwmxsocb adc action qualifier (aq) epwma dead band (db) epwmb pwm chopper (pc) trip zone (tz) epwmxa epwmxb ctr=zero epwmxtzint tz1 tz3 to emustop clockfail eqep1err (b) dcaevt1.force (a) dcaevt2.force (a) dcbevt1.force (a) dcbevt2.force (a) ctr=cmpa 16 cmpahr (8) ctr=cmpb 16 cmpb active (16) cmpb shadow (16) high-resolution pwm (hrpwm) ctr=prd or zero dcaevt1.inter dcbevt1.interdcaevt2.inter dcbevt2.inter epwmxsynci tbctl[swfsync](software forced sync) dcaevt1.sync dcbevt1.sync cmpa active (24) cmpa shadow (24)
132 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.9.1 epwm electrical data/timing pwm refers to pwm outputs on epwm1 ? 8. table 6-58 shows the pwm timing requirements and table 6- 59 , switching characteristics. (1) for an explanation of the input qualifier parameters, see table 6-76 . table 6-58. epwm timing requirements (1) min max unit t w(sycin) sync input pulse width asynchronous 2t c(sco) cycles synchronous 2t c(sco) cycles with input qualifier 1t c(sco) + t w(iqsw) cycles table 6-59. epwm switching characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min max unit t w(pwm) pulse duration, pwmx output high/low 33.33 ns t w(syncout) sync output pulse width 8t c(sco) cycles t d(pwm)tza delay time, trip input active to pwm forced high delay time, trip input active to pwm forced low no pin load 25 ns t d(tz-pwm)hz delay time, trip input active to pwm hi-z 20 ns 6.9.9.2 trip-zone input timing (1) for an explanation of the input qualifier parameters, see table 6-76 . table 6-60. trip-zone input timing requirements (1) min max unit t w(tz) pulse duration, tzx input low asynchronous 2t c(tbclk) cycles synchronous 2t c(tbclk) cycles with input qualifier 2t c(tbclk) + t w(iqsw) cycles a. tz - tz1, tz2, tz3, tz4, tz5, tz6 b. pwm refers to all the pwm pins in the device. the state of the pwm pins after tz is taken high depends on the pwm recovery software. figure 6-50. pwm hi-z characteristics pwm (b) tz (a) sysclk t w(tz) t d(tz-pwm)hz
133 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) the hrpwm operates at a minimum sysclkout frequency of 60 mhz. (2) maximum mep step size is based on worst-case process, maximum temperature and minimum voltage. mep step size will increase with low voltage and high temperature and decrease with voltage and cold temperature. applications that use the hrpwm feature should use mep scale factor optimizer (sfo) estimation software functions. see the ti software libraries for details of using sfo function in end applications. sfo functions help to estimate the number of mep steps per sysclkout period dynamically while the hrpwm is in operation. 6.9.10 high-resolution pwm (hrpwm) this module combines multiple delay lines in a single module and a simplified calibration system by using a dedicated calibration delay line. for each epwm module there is one hr delay line. the hrpwm module offers pwm resolution (time granularity) that is significantly better than what can be achieved using conventionally derived digital pwm methods. the key points for the hrpwm module are: ? significantly extends the time resolution capabilities of conventionally derived digital pwm ? this capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge control for frequency/period modulation. ? finer time granularity control or edge positioning is controlled through extensions to the compare a and phase registers of the epwm module. ? hrpwm capabilities, when available on a particular device, are offered only on the a signal path of an epwm module (that is, on the epwmxa output). epwmxb output has conventional pwm capabilities. note the minimum sysclkout frequency allowed for hrpwm is 60 mhz. note when dual-edge high-resolution is enabled (high-resolution period mode), the pwmxb channel will have 1 ? 2 tbclk cycles of jitter on the output. 6.9.10.1 hrpwm electrical data/timing table 6-61 shows the high-resolution pwm switching characteristics. table 6-61. high-resolution pwm characteristics (1) parameter min typ max unit micro edge positioning (mep) step size (2) 150 310 ps
134 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.11 enhanced capture module (ecap1) the device contains an enhanced capture (ecap) module. figure 6-51 shows a functional block diagram of a module. figure 6-51. ecap functional block diagram the ecap module is clocked at the sysclkout rate. the clock enable bits (ecap1 enclk) in the pclkcr1 register turn off the ecap module individually (for low-power operation). upon reset, ecap1enclk is set to low, indicating that the peripheral clock is off. tsctr (counter?32 bit) rst cap1 (aprd active) ld cap2 (acmp active) ld cap3 (aprd shadow) ld cap4 (acmp shadow) ld continuous / oneshot capture control ld1ld2 ld3ld4 32 32 prd [0?31] cmp [0?31] ctr [0?31] ecapx interrupt trigger and flag control to pie ctr=cmp 32 32 32 32 32 acmp shadow event pre-scale ctrphs (phase register?32 bit) syncout syncin event qualifier polarity select polarity select polarity select polarity select ctr=prd ctr_ovf 4 pwm compare logic ctr [0?31] prd [0?31] cmp [0?31] ctr=cmp ctr=prd ctr_ovf ovf apwm mode delta?mode sync 4 capture events cevt[1:4] aprd shadow 32 32 mode select
135 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated table 6-62. ecap control and status registers name ecap1 ecap2 ecap3 size ( 16) eallow protected description tsctr 0x6a00 0x6a20 0x6a40 2 no time-stamp counter ctrphs 0x6a02 0x6a22 0x6a42 2 no counter phase offset value register cap1 0x6a04 0x6a24 0x6a44 2 no capture 1 register cap2 0x6a06 0x6a26 0x6a46 2 no capture 2 register cap3 0x6a08 0x6a28 0x6a48 2 no capture 3 register cap4 0x6a0a 0x6a2a 0x6a4a 2 no capture 4 register reserved 0x6a0c ? 0x6a12 0x6a2c ? 0x6a32 0x6a4c ? 0x6a52 8 no reserved ecctl1 0x6a14 0x6a34 0x6a54 1 no capture control register 1 ecctl2 0x6a15 0x6a35 0x6a55 1 no capture control register 2 eceint 0x6a16 0x6a36 0x6a56 1 no capture interrupt enable register ecflg 0x6a17 0x6a37 0x6a57 1 no capture interrupt flag register ecclr 0x6a18 0x6a38 0x6a58 1 no capture interrupt clear register ecfrc 0x6a19 0x6a39 0x6a59 1 no capture interrupt force register reserved 0x6a1a ? 0x6a1f 0x6a3a ? 0x6a3f 0x6a5a ? 0x6a5f 6 no reserved 6.9.11.1 ecap electrical data/timing table 6-63 shows the ecap timing requirement and table 6-64 shows the ecap switching characteristics. (1) for an explanation of the input qualifier parameters, see table 6-76 . table 6-63. enhanced capture (ecap) timing requirement (1) min max unit t w(cap) capture input pulse width asynchronous 2t c(sco) cycles synchronous 2t c(sco) with input qualifier 1t c(sco) + t w(iqsw) table 6-64. ecap switching characteristics over recommended operating conditions (unless otherwise noted) parameter min max unit t w(apwm) pulse duration, apwmx output high/low 20 ns
136 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.12 high-resolution capture modules (hrcap1 ? hrcap4) the device contains up to four high-resolution capture (hrcap) modules. the high-resolution capture (hrcap) module measures the difference between external pulses with a typical resolution of 300 ps. uses for the hrcap include: ? capactive touch applications ? high-resolution period and duty cycle measurements of pulse train cycles ? instantaneous speed measurements ? instantaneous frequency measurements ? voltage measurements across an isolation boundary ? distance measurement (sonar) and scanning the hrcap module features include: ? pulse width capture in either non-high-resolution or high-resolution modes ? difference (delta) mode pulse width capture ? typical high-resolution capture on the order of 300 ps resolution on each edge ? interrupt on either falling or rising edge ? continuous mode capture of pulse widths in 2-deep buffer ? calibration logic for precision high-resolution capture ? all of the above resources are dedicated to a single input pin ? hrcap calibration software library supplied by ti is used for both calibration and calculating fractional pulse widths the hrcap module includes one capture channel in addition to a high-resolution calibration block, which connects internally to the last available epwmxa hrpwm channel when calibrating (that is, if there are eight epwms with hrpwm capability, it will be hrpwm8a). each hrcap channel has the following independent key resources: ? dedicated input capture pin ? 16-bit hrcap clock which is either equal to the pll2 output frequency (asynchronous to sysclk2) or equal to the sysclk2 frequency (synchronous to sysclk2) ? high-resolution pulse width capture in a 2-deep buffer figure 6-52. hrcap functional block diagram pie hrcapx sysclk2 pll2clk hrcapxenclk hrcapxintn hrcap calibration logic epwmxa epwmx hrpwm hrcap calibration signal (internal) gpio mux hrcapx module
137 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) registers that are eallow-protected. table 6-65. hrcap registers name hrcap1 hrcap2 hrcap3 hrcap4 size ( 16) description hcctl 0x6ac0 0x6ae0 0x6c80 0x6ca0 1 hrcap control register (1) hcifr 0x6ac1 0x6ae1 0x6c81 0x6ca1 1 hrcap interrupt flag register hciclr 0x6ac2 0x6ae2 0x6c82 0x6ca2 1 hrcap interrupt clear register (1) hcifrc 0x6ac3 0x6ae3 0x6c83 0x6ca3 1 hrcap interrupt force register (1) hccounter 0x6ac4 0x6ae4 0x6c84 0x6ca4 1 hrcap 16-bit counter register hccapcntrise0 0x6ad0 0x6af0 0x6c90 0x6cb0 1 hrcap capture counter on rising edge 0 register hccapcntfall0 0x6ad2 0x6af2 0x6c92 0x6cb2 1 hrcap capture counter on falling edge 0 register hccapcntrise1 0x6ad8 0x6af8 0x6c98 0x6cb8 1 hrcap capture counter on rising edge 1 register hccapcntfall1 0x6ada 0x6afa 0x6c9a 0x6cba 1 hrcap capture counter on falling edge 1 register 6.9.12.1 hrcap electrical data/timing (1) the listed minimum pulse width does not take into account the limitation that all relevant hccap registers must be read and rise/fall event flags cleared within the pulse width to ensure valid capture data. (2) hrcap step size will increase with low voltage and high temperature and decrease with high voltage and low temperature. applications that use the hrcap in high-resolution mode should use the hrcap calibration functions to dynamically calibrate for varying operating conditions. table 6-66. high-resolution capture (hrcap) timing requirements min nom max unit t c(hccapclk) cycle time, hrcap capture clock 8.333 10.204 ns t w(hrcap) pulse width, hrcap capture 7t c(hccapclk) (1) ns hrcap step size (2) 300 ps
138 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.13 enhanced quadrature encoder modules (eqep1, eqep2) the device contains up to two enhanced quadrature encoder (eqep) modules. table 6-67 provides a summary of the eqep registers. table 6-67. eqep control and status registers name eqep1 address eqep2 address eqep1 size( 16)/ #shadow register description qposcnt 0x6b00 0x6b40 2/0 eqep position counter qposinit 0x6b02 0x6b42 2/0 eqep initialization position count qposmax 0x6b04 0x6b44 2/0 eqep maximum position count qposcmp 0x6b06 0x6b46 2/1 eqep position-compare qposilat 0x6b08 0x6b48 2/0 eqep index position latch qposslat 0x6b0a 0x6b4a 2/0 eqep strobe position latch qposlat 0x6b0c 0x6b4c 2/0 eqep position latch qutmr 0x6b0e 0x6b4e 2/0 eqep unit timer quprd 0x6b10 0x6b50 2/0 eqep unit period register qwdtmr 0x6b12 0x6b52 1/0 eqep watchdog timer qwdprd 0x6b13 0x6b53 1/0 eqep watchdog period register qdecctl 0x6b14 0x6b54 1/0 eqep decoder control register qepctl 0x6b15 0x6b55 1/0 eqep control register qcapctl 0x6b16 0x6b56 1/0 eqep capture control register qposctl 0x6b17 0x6b57 1/0 eqep position-compare control register qeint 0x6b18 0x6b58 1/0 eqep interrupt enable register qflg 0x6b19 0x6b59 1/0 eqep interrupt flag register qclr 0x6b1a 0x6b5a 1/0 eqep interrupt clear register qfrc 0x6b1b 0x6b5b 1/0 eqep interrupt force register qepsts 0x6b1c 0x6b5c 1/0 eqep status register qctmr 0x6b1d 0x6b5d 1/0 eqep capture timer qcprd 0x6b1e 0x6b5e 1/0 eqep capture period register qctmrlat 0x6b1f 0x6b5f 1/0 eqep capture timer latch qcprdlat 0x6b20 0x6b60 1/0 eqep capture period latch reserved 0x6b21 ? 0x6b3f 0x6b61 ? 0x6b7f 31/0
139 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated figure 6-53 shows the block diagram of the eqep module. figure 6-53. eqep functional block diagram qwdtmr qwdprd 16 qwdog utime quprd qutmr 32 utout wdtout quadrature capture unit (qcap) qcprdlat qctmrlat 16 qflg qepsts qepctl registers used by multiple units qclk qdir qi qs phe pcsout quadrature decoder (qdu) qdecctl 16 position counter/ control unit (pccu) qposlat qposslat 16 qposilat eqepxaineqepxbin eqepxiin eqepxiout eqepxioe eqepxsin eqepxsout eqepxsoe gpio mux eqepxa/xclk eqepxb/xdir eqepxs eqepxi qposcmp qeint qfrc 32 qclr qposctl 16 32 qposcnt qposmax qposinit pie eqepxint enhanced qep (eqep) peripheral system control registers qctmr qcprd 16 16 qcapctl eqepxenclk sysclkout to cpu data bus
140 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.13.1 eqep electrical data/timing table 6-68 shows the eqep timing requirement and table 6-69 shows the eqep switching characteristics. (1) for an explanation of the input qualifier parameters, see table 6-76 . (2) refer to the tms320f28069, tms320f28068, tms320f28067, tms320f28066, tms320f28065, tms320f28064, tms320f28063, tms320f28062 piccolo mcus silicon errata ( sprz342 ) for limitations in the asynchronous mode. table 6-68. enhanced quadrature encoder pulse (eqep) timing requirements (1) min max unit t w(qepp) qep input period asynchronous (2) /synchronous 2t c(sco) cycles with input qualifier 2[1t c(sco) + t w(iqsw) ] t w(indexh) qep index input high time asynchronous (2) /synchronous 2t c(sco) cycles with input qualifier 2t c(sco) +t w(iqsw) t w(indexl) qep index input low time asynchronous (2) /synchronous 2t c(sco) cycles with input qualifier 2t c(sco) + t w(iqsw) t w(strobh) qep strobe high time asynchronous (2) /synchronous 2t c(sco) cycles with input qualifier 2t c(sco) + t w(iqsw) t w(strobl) qep strobe input low time asynchronous (2) /synchronous 2t c(sco) cycles with input qualifier 2t c(sco) +t w(iqsw) table 6-69. eqep switching characteristics over recommended operating conditions (unless otherwise noted) parameter min max unit t d(cntr)xin delay time, external clock to counter increment 4t c(sco) cycles t d(pcs-out)qep delay time, qep input edge to position compare sync output 6t c(sco) cycles
141 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.14 jtag port on the 2806x device, the jtag port is reduced to 5 pins ( trst, tck, tdi, tms, tdo). tck, tdi, tms and tdo pins are also gpio pins. the trst signal selects either jtag or gpio operating mode for the pins in figure 6-54 . during emulation/debug, the gpio function of these pins are not available. if the gpio38/tck/xclkin pin is used to provide an external clock, an alternate clock source should be used to clock the device during emulation/debug because this pin will be needed for the tck function. note in 2806x devices, the jtag pins may also be used as gpio pins. care should be taken in the board design to ensure that the circuitry connected to these pins do not affect the emulation capabilities of the jtag pin function. any circuitry connected to these pins should not prevent the emulator from driving (or being driven by) the jtag pins for successful debug. figure 6-54. jtag/gpio multiplexing trst 1 0 c28x core tck/gpio38 tck xclkin gpio38_in gpio38_out tdo gpio37_out tdo/gpio37 gpio37_in 1 0 tms tms/gpio36 gpio36_out gpio36_in 1 1 0 tdi tdi/gpio35 gpio35_out gpio35_in 1 trsttrst = 0: jtag disabled (gpio mode) = 1: jtag mode trst
142 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.15 general-purpose input/output (gpio) mux the gpio mux can multiplex up to three independent peripheral signals on a single gpio pin in addition to providing individual pin bit-banging i/o capability. the device supports 45 gpio pins. the gpio control and data registers are mapped to peripheral frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). table 6-70 shows the gpio register mapping. table 6-70. gpio registers name address size ( 16) description gpio control registers (eallow protected) gpactrl 0x6f80 2 gpio a control register (gpio0 to 31) gpaqsel1 0x6f82 2 gpio a qualifier select 1 register (gpio0 to 15) gpaqsel2 0x6f84 2 gpio a qualifier select 2 register (gpio16 to 31) gpamux1 0x6f86 2 gpio a mux 1 register (gpio0 to 15) gpamux2 0x6f88 2 gpio a mux 2 register (gpio16 to 31) gpadir 0x6f8a 2 gpio a direction register (gpio0 to 31) gpapud 0x6f8c 2 gpio a pull up disable register (gpio0 to 31) gpbctrl 0x6f90 2 gpio b control register (gpio32 to 44) gpbqsel1 0x6f92 2 gpio b qualifier select 1 register (gpio32 to 44) gpbqsel2 0x6f94 2 gpio b qualifier select 2 register gpbmux1 0x6f96 2 gpio b mux 1 register (gpio32 to 44) gpbmux2 0x6f98 2 gpio b mux 2 register (gpio50 to 58) gpbdir 0x6f9a 2 gpio b direction register (gpio32 to 44) gpbpud 0x6f9c 2 gpio b pull up disable register (gpio32 to 44) aiomux1 0x6fb6 2 analog, i/o mux 1 register (aio0 to aio15) aiodir 0x6fba 2 analog, i/o direction register (aio0 to aio15) gpio data registers (not eallow protected) gpadat 0x6fc0 2 gpio a data register (gpio0 to 31) gpaset 0x6fc2 2 gpio a data set register (gpio0 to 31) gpaclear 0x6fc4 2 gpio a data clear register (gpio0 to 31) gpatoggle 0x6fc6 2 gpio a data toggle register (gpio0 to 31) gpbdat 0x6fc8 2 gpio b data register (gpio32 to 44) gpbset 0x6fca 2 gpio b data set register (gpio32 to 44) gpbclear 0x6fcc 2 gpio b data clear register (gpio32 to 44) gpbtoggle 0x6fce 2 gpio b data toggle register (gpio32 to 44) aiodat 0x6fd8 2 analog i/o data register (aio0 to aio15) aioset 0x6fda 2 analog i/o data set register (aio0 to aio15) aioclear 0x6fdc 2 analog i/o data clear register (aio0 to aio15) aiotoggle 0x6fde 2 analog i/o data toggle register (aio0 to aio15) gpio interrupt and low power modes select registers (eallow protected) gpioxint1sel 0x6fe0 1 xint1 gpio input select register (gpio0 to 31) gpioxint2sel 0x6fe1 1 xint2 gpio input select register (gpio0 to 31) gpioxint3sel 0x6fe2 1 xint3 gpio input select register (gpio0 to 31) gpiolpmsel 0x6fe8 2 lpm gpio select register (gpio0 to 31) note there is a two-sysclkout cycle delay from when the write to the gpxmuxn/aiomuxn and gpxqseln registers occurs to when the action is valid.
143 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) the word " reserved " means that there is no peripheral assigned to this gpxmux1/2 register setting. should it be selected, the state of the pin will be undefined and the pin may be driven. this selection is a reserved configuration for future expansion. (2) i = input, o = output, od = open drain (3) the eqep2 peripheral is not available on the 80-pin pn or pfp package. table 6-71. gpioa mux (1) (2) default at reset primary i/o function peripheral selection 1 peripheral selection 2 peripheral selection 3 gpamux1 register bits (gpamux1 bits = 00) (gpamux1 bits = 01) (gpamux1 bits = 10) (gpamux1 bits = 11) 1-0 gpio0 epwm1a (o) reserved reserved 3-2 gpio1 epwm1b (o) reserved comp1out (o) 5-4 gpio2 epwm2a (o) reserved reserved 7-6 gpio3 epwm2b (o) spisomia (i/o) comp2out (o) 9-8 gpio4 epwm3a (o) reserved reserved 11-10 gpio5 epwm3b (o) spisimoa (i/o) ecap1 (i/o) 13-12 gpio6 epwm4a (o) epwmsynci (i) epwmsynco (o) 15-14 gpio7 epwm4b (o) scirxda (i) ecap2 (i/o) 17-16 gpio8 epwm5a (o) reserved adcsocao (o) 19-18 gpio9 epwm5b (o) scitxdb (o) ecap3 (i/o) 21-20 gpio10 epwm6a (o) reserved adcsocbo (o) 23-22 gpio11 epwm6b (o) scirxdb (i) ecap1 (i/o) 25-24 gpio12 tz1 (i) scitxda (o) spisimob (i/o) 27-26 gpio13 tz2 (i) reserved spisomib (i/o) 29-28 gpio14 tz3 (i) scitxdb (o) spiclkb (i/o) 31-30 gpio15 ecap2 (i/o) scirxdb (i) spisteb (i/o) gpamux2 register bits (gpamux2 bits = 00) (gpamux2 bits = 01) (gpamux2 bits = 10) (gpamux2 bits = 11) 1-0 gpio16 spisimoa (i/o) reserved tz2 (i) 3-2 gpio17 spisomia (i/o) reserved tz3 (i) 5-4 gpio18 spiclka (i/o) scitxdb (o) xclkout (o) 7-6 gpio19/xclkin spistea (i/o) scirxdb (i) ecap1 (i/o) 9-8 gpio20 eqep1a (i) mdxa (o) comp1out (o) 11-10 gpio21 eqep1b (i) mdra (i) comp2out (o) 13-12 gpio22 eqep1s (i/o) mclkxa (i/o) scitxdb (o) 15-14 gpio23 eqep1i (i/o) mfsxa (i/o) scirxdb (i) 17-16 gpio24 ecap1 (i/o) eqep2a (3) (i) spisimob (i/o) 19-18 gpio25 ecap2 (i/o) eqep2b (3) (i) spisomib (i/o) 21-20 gpio26 ecap3 (i/o) eqep2i (3) (i/o) spiclkb (i/o) 23-22 gpio27 hrcap2 (i) eqep2s (3) (i/o) spisteb (i/o) 25-24 gpio28 scirxda (i) sdaa (i/od) tz2 (i) 27-26 gpio29 scitxda (o) scla (i/od) tz3 (i) 29-28 gpio30 canrxa (i) eqep2i (3) (i/o) epwm7a (o) 31-30 gpio31 cantxa (o) eqep2s (3) (i/o) epwm8a (o)
144 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) the word " reserved " means that there is no peripheral assigned to this gpxmux1/2 register setting. should it be selected, the state of the pin will be undefined and the pin may be driven. this selection is a reserved configuration for future expansion. (2) i = input, o = output, od = open drain (3) this pin is not available in the 80-pin pn or pfp package. table 6-72. gpiob mux (1) (2) default at reset primary i/o function peripheral selection 1 peripheral selection 2 peripheral selection 3 gpbmux1 register bits (gpbmux1 bits = 00) (gpbmux1 bits = 01) (gpbmux1 bits = 10) (gpbmux1 bits = 11) 1-0 gpio32 sdaa (i/od) epwmsynci (i) adcsocao (o) 3-2 gpio33 scla (i/od) epwmsynco (o) adcsocbo (o) 5-4 gpio34 comp2out (o) reserved comp3out (o) 7-6 gpio35 (tdi) reserved reserved reserved 9-8 gpio36 (tms) reserved reserved reserved 11-10 gpio37 (tdo) reserved reserved reserved 13-12 gpio38/xclkin (tck) reserved reserved reserved 15-14 gpio39 reserved reserved reserved 17-16 gpio40 (3) epwm7a (o) scitxdb (o) reserved 19-18 gpio41 (3) epwm7b (o) scirxdb (i) reserved 21-20 gpio42 (3) epwm8a (o) tz1 (i) comp1out (o) 23-22 gpio43 (3) epwm8b (o) tz2 (i) comp2out (o) 25-24 gpio44 (3) mfsra (i/o) scirxdb (i) epwm7b (o) 27-26 reserved reserved reserved reserved 29-28 reserved reserved reserved reserved 31-30 reserved reserved reserved reserved gpbmux2 register bits (gpbmux2 bits = 00) (gpbmux2 bits = 01) (gpbmux2 bits = 10) (gpbmux2 bits = 11) 1-0 reserved reserved reserved reserved 3-2 reserved reserved reserved reserved 5-4 gpio50 (3) eqep1a (i) mdxa (o) tz1 (i) 7-6 gpio51 (3) eqep1b (i) mdra (i) tz2 (i) 9-8 gpio52 (3) eqep1s (i/o) mclkxa (i/o) tz3 (i) 11-10 gpio53 (3) eqep1i (i/o) mfsxa (i/o) reserved 13-12 gpio54 (3) spisimoa (i/o) eqep2a (i) hrcap1 (i) 15-14 gpio55 (3) spisomia (i/o) eqep2b (i) hrcap2 (i) 17-16 gpio56 (3) spiclka (i/o) eqep2i (i/o) hrcap3 (i) 19-18 gpio57 (3) spistea (i/o) eqep2s (i/o) hrcap4 (i) 21-20 gpio58 (3) mclkra (i/o) scitxdb (o) epwm7a (o) 23-22 reserved reserved reserved reserved 25-24 reserved reserved reserved reserved 27-26 reserved reserved reserved reserved 29-28 reserved reserved reserved reserved 31-30 reserved reserved reserved reserved
145 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) i = input, o = output table 6-73. analog mux for 100-pin pz and 100-pin pzp packages (1) default at reset aiox and peripheral selection 1 peripheral selection 2 and peripheral selection 3 aiomux1 register bits aiomux1 bits = 0,x aiomux1 bits = 1,x 1-0 adcina0 (i) adcina0 (i) 3-2 adcina1 (i) adcina1 (i) 5-4 aio2 (i/o) adcina2 (i), comp1a (i) 7-6 adcina3 (i) adcina3 (i) 9-8 aio4 (i/o) adcina4 (i), comp2a (i) 11-10 adcina5 (i) adcina5 (i) 13-12 aio6 (i/o) adcina6 (i), comp3a (i) 15-14 adcina7 (i) adcina7 (i) 17-16 adcinb0 (i) adcinb0 (i) 19-18 adcinb1 (i) adcinb1 (i) 21-20 aio10 (i/o) adcinb2 (i), comp1b (i) 23-22 adcinb3 (i) adcinb3 (i) 25-24 aio12 (i/o) adcinb4 (i), comp2b (i) 27-26 adcinb5 (i) adcinb5 (i) 29-28 aio14 (i/o) adcinb6 (i), comp3b (i) 31-30 adcinb7 (i) adcinb7 (i) (1) i = input, o = output table 6-74. analog mux for 80-pin pn and 80-pin pfp packages (1) default at reset aiox and peripheral selection 1 peripheral selection 2 and peripheral selection 3 aiomux1 register bits aiomux1 bits = 0,x aiomux1 bits = 1,x 1-0 adcina0 (i), v refhi (i) adcina0 (i), v refhi (i) 3-2 adcina1 (i) adcina1 (i) 5-4 aio2 (i/o) adcina2 (i), comp1a (i) 7-6 ? ? 9-8 aio4 (i/o) adcina4 (i), comp2a (i) 11-10 adcina5 (i) adcina5 (i) 13-12 aio6 (i/o) adcina6 (i), comp3a (i) 15-14 ? ? 17-16 adcinb0 (i) adcinb0 (i) 19-18 adcinb1 (i) adcinb1 (i) 21-20 aio10 (i/o) adcinb2 (i), comp1b (i) 23-22 ? ? 25-24 aio12 (i/o) adcinb4 (i), comp2b (i) 27-26 adcinb5 (i) adcinb5 (i) 29-28 aio14 (i/o) adcinb6 (i), comp3b (i) 31-30 ? ?
146 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated the user can select the type of input qualification for each gpio pin through the gpxqsel1/2 registers from four choices: ? synchronization to sysclkout only (gpxqsel1/2 = 0, 0): this is the default mode of all gpio pins at reset and it simply synchronizes the input signal to the system clock (sysclkout). ? qualification using sampling window (gpxqsel1/2 = 0, 1 and 1, 0): in this mode the input signal, after synchronization to the system clock (sysclkout), is qualified by a specified number of cycles before the input is allowed to change. ? the sampling period is specified by the qualprd bits in the gpxctrl register and is configurable in groups of 8 signals. the sampling period specifies a multiple of sysclkout cycles for sampling the input signal. the sampling window is either 3-samples or 6-samples wide and the output is only changed when all samples are the same (all 0s or all 1s) as shown in figure 4-18 (for 6 sample mode). ? no synchronization (gpxqsel1/2 = 1,1): this mode is used for peripherals where synchronization is not required (synchronization is performed within the peripheral). due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral input signal can be mapped to more then one gpio pin. also, when an input signal is not selected, the input signal will default to either a 0 or 1 state, depending on the peripheral.
147 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated a. x stands for the port, either a or b. for example, gpxdir refers to either the gpadir and gpbdir register depending on the particular gpio pin selected. b. gpxdat latch/read are accessed at the same memory location. c. this is a generic gpio mux block diagram. not all options may be applicable for all gpio pins. see the systems control and interrupts chapter of the tms320x2806x piccolo technical reference manual ( spruh18 ) for pin-specific variations. figure 6-55. gpio multiplexing gpxdat (read) input qualification gpxmux1/2 high impedance output control gpiox pin xrs 0 = input, 1 = output low p ower modes block gpxdir (latch) peripheral 2 input peripheral 3 input peripheral 1 output peripheral 2 output peripheral 3 output peripheral 1 output enable peripheral 2 output enable peripheral 3 output enable 00 01 10 11 0001 10 11 00 01 10 11 gpxctrl peripheral 1 input n/c gpxpud lpmcr0 internal pullup gpiolmpsel gpxqsel1/2 gpxset gpxdat (latch) gpxclear gpxtoggle = default at reset pie external interrupt mux asynchronous path asynchronous path gpioxint1sel gpioxint2sel gpioxint3sel
148 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.15.1 gpio electrical data/timing 6.9.15.1.1 gpio output timing table 6-75. general-purpose output switching characteristics over recommended operating conditions (unless otherwise noted) parameter min max unit t r(gpo) rise time, gpio switching low to high all gpios 13 (1) ns t f(gpo) fall time, gpio switching high to low all gpios 13 (1) ns f gpo toggling frequency 22.5 mhz (1) rise time and fall time vary with electrical loading on i/o pins. values given in table 6-75 are applicable for a 40-pf load on i/o pins. figure 6-56. general-purpose output timing gpio t r(gpo) t f(gpo)
149 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.15.1.2 gpio input timing (1) " n " represents the number of qualification samples as defined by gpxqseln register. (2) for t w(gpi) , pulse width is measured from v il to v il for an active-low signal and v ih to v ih for an active-high signal. table 6-76. general-purpose input timing requirements min max unit t w(sp) sampling period qualprd = 0 1t c(sco) cycles qualprd 0 2t c(sco) * qualprd t w(iqsw) input qualifier sampling window t w(sp) * (n (1) ? 1) cycles t w(gpi) (2) pulse duration, gpio low/high synchronous mode 2t c(sco) cycles with input qualifier t w(iqsw) + t w(sp) + 1t c(sco) a. this glitch will be ignored by the input qualifier. the qualprd bit field specifies the qualification sampling period. the qualprd bit field value can vary from 00 to 0xff. if qualprd = 00, then the sampling period is one sysclkout cycle. for any other value " n " , the qualification sampling period in 2n sysclkout cycles (that is, at every 2n sysclkout cycles, the gpio pin will be sampled). b. the qualification period selected through the gpxctrl register applies to groups of 8 gpio pins. c. the qualification block can take either three or six samples. the gpxqseln register selects which sample mode is used. d. in the example shown, for the qualifier to detect the change, the input should be stable for 10 sysclkout cycles or greater. in other words, the inputs should be stable for (5 qualprd 2) sysclkout cycles. this would ensure 5 sampling periods for detection to occur. because external signals are driven asynchronously, an 13-sysclkout- wide pulse ensures reliable recognition. figure 6-57. sampling mode gpio signal 1 sampling window output from qualifier 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 sysclkout qualprd = 1 (sysclkout/2) (a) gpxqseln = 1,0 (6 samples) [(sysclkout cycle * 2 * qualprd) * 5 ] (c) sampling period determinedby gpxctrl[qualprd] (b) (d) t w(sp) t w(iqsw)
150 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.15.1.3 sampling window width for input signals the following section summarizes the sampling window width for input signals for various input qualifier configurations. sampling frequency denotes how often a signal is sampled with respect to sysclkout. sampling frequency = sysclkout/(2 * qualprd), if qualprd 0 sampling frequency = sysclkout, if qualprd = 0 sampling period = sysclkout cycle 2 qualprd, if qualprd 0 in the above equations, sysclkout cycle indicates the time period of sysclkout. sampling period = sysclkout cycle, if qualprd = 0 in a given sampling window, either three or six samples of the input signal are taken to determine the validity of the signal. this is determined by the value written to gpxqseln register. case 1: qualification using three samples sampling window width = (sysclkout cycle 2 qualprd) 2, if qualprd 0 sampling window width = (sysclkout cycle) 2, if qualprd = 0 case 2: qualification using six samples sampling window width = (sysclkout cycle 2 qualprd) 5, if qualprd 0 sampling window width = (sysclkout cycle) 5, if qualprd = 0 figure 6-58. general-purpose input timing figure 6-59. input resistance model for a gpio pin with an internal pullup v ddio v ss v ss 2 pf > 1 m s gpioxn sysclk t w(gpi)
151 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.15.1.4 low-power mode wakeup timing table 6-77 shows the timing requirements, table 6-78 shows the switching characteristics, and figure 6- 60 shows the timing diagram for idle mode. (1) for an explanation of the input qualifier parameters, see table 6-76 . table 6-77. idle mode timing requirements (1) min max unit t w(wake-int) pulse duration, external wake-up signal without input qualifier 2t c(sco) cycles with input qualifier 5t c(sco) + t w(iqsw) (1) for an explanation of the input qualifier parameters, see table 6-76 . (2) this is the time taken to begin execution of the instruction that immediately follows the idle instruction. execution of an isr (triggered by the wake-up) signal involves additional latency. table 6-78. idle mode switching characteristics (1) over recommended operating conditions (unless otherwise noted) parameter test conditions min max unit t d(wake-idle) delay time, external wake signal to program execution resume (2) cycles ? wake-up from flash ? flash module in active state without input qualifier 20t c(sco) cycles with input qualifier 20t c(sco) + t w(iqsw) ? wake-up from flash ? flash module in sleep state without input qualifier 1050t c(sco) cycles with input qualifier 1050t c(sco) + t w(iqsw) ? wake-up from saram without input qualifier 20t c(sco) cycles with input qualifier 20t c(sco) + t w(iqsw) a. wake int can be any enabled interrupt, wdint or xrs. after the idle instruction is executed, a delay of five oscclk cycles (minimum) is needed before the wake-up signal could be asserted. b. from the time the idle instruction is executed to place the device into low-power mode (lpm), wakeup should not be initiated until at least four oscclk cycles have elapsed. figure 6-60. idle entry and exit timing wake int (a)(b) xclkout address/data (internal) t d(wake?idle) t w(wake?int)
152 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated (1) qualstdby is a 6-bit field in the lpmcr0 register. table 6-79. standby mode timing requirements min max unit t w(wake- int) pulse duration, external wake-up signal without input qualification 3t c(oscclk) cycles with input qualification (1) (2 + qualstdby) * t c(oscclk) (1) this is the time taken to begin execution of the instruction that immediately follows the idle instruction. execution of an isr (triggered by the wake up signal) involves additional latency. table 6-80. standby mode switching characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min max unit t d(idle-xcol) delay time, idle instruction executed to xclkout low 32t c(sco) 45t c(sco) cycles t d(wake-stby) delay time, external wake signal to program execution resume (1) cycles ? wake up from flash ? flash module in active state without input qualifier 100t c(sco) cycles with input qualifier 100t c(sco) + t w(wake-int) ? wake up from flash ? flash module in sleep state without input qualifier 1125t c(sco) cycles with input qualifier 1125t c(sco) + t w(wake-int) ? wake up from saram without input qualifier 100t c(sco) cycles with input qualifier 100t c(sco) + t w(wake-int)
153 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated a. idle instruction is executed to put the device into standby mode. b. the pll block responds to the standby signal. sysclkout is held for the number of cycles indicated below before being turned off: ? 16 cycles, when divsel = 00 or 01 ? 32 cycles, when divsel = 10 ? 64 cycles, when divsel = 11 this delay enables the cpu pipeline and any other pending operations to flush properly. c. clock to the peripherals are turned off. however, the pll and watchdog are not shut down. the device is now in standby mode. after the idle instruction is executed, a delay of five oscclk cycles (minimum) is needed before the wake-up signal could be asserted. d. the external wake-up signal is driven active. e. the wake-up signal fed to a gpio pin to wake up the device must meet the minimum pulse width requirement. furthermore, this signal must be free of glitches. if a noisy signal is fed to a gpio pin, the wake-up behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses. f. after a latency period, the standby mode is exited. g. normal execution resumes. the device will respond to the interrupt (if enabled). h. from the time the idle instruction is executed to place the device into low-power mode (lpm), wakeup should not be initiated until at least four oscclk cycles have elapsed. figure 6-61. standby entry and exit timing diagram table 6-81. halt mode timing requirements min max unit t w(wake-gpio) pulse duration, gpio wake-up signal t oscst + 2t c(oscclk) cycles t w(wake-xrs) pulse duration, xrs wakeup signal t oscst + 8t c(oscclk) cycles table 6-82. halt mode switching characteristics over recommended operating conditions (unless otherwise noted) parameter min max unit t d(idle-xcol) delay time, idle instruction executed to xclkout low 32t c(sco) 45t c(sco) cycles t p pll lock-up time 1 ms t d(wake-halt) delay time, pll lock to program execution resume ? wake up from flash ? flash module in sleep state 1125t c(sco) cycles ? wake up from saram 35t c(sco) cycles t d(idle?xcol) wake-up signal (h) x1/x2 or xclkin xclkout flushing pipeline (a) device status standby normal execution standby (g) (b) (c) (d)(e) (f) t w(wake-int) t d(wake-stby)
154 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated a. idle instruction is executed to put the device into halt mode. b. the pll block responds to the halt signal. sysclkout is held for the number of cycles indicated below before oscillator is turned off and the clkin to the core is stopped: ? 16 cycles, when divsel = 00 or 01 ? 32 cycles, when divsel = 10 ? 64 cycles, when divsel = 11 this delay enables the cpu pipeline and any other pending operations to flush properly. c. clocks to the peripherals are turned off and the pll is shut down. if a quartz crystal or ceramic resonator is used as the clock source, the internal oscillator is shut down as well. the device is now in halt mode and consumes absolute minimum power. it is possible to keep the zero-pin internal oscillators (intosc1 and intosc2) and the watchdog alive in halt mode. this is done by writing to the appropriate bits in the clkctl register. after the idle instruction is executed, a delay of five oscclk cycles (minimum) is needed before the wake-up signal could be asserted. d. when the gpion pin (used to bring the device out of halt) is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. the gpio pin should be driven high only after the oscillator has stabilized. this enables the provision of a clean clock signal during the pll lock sequence. because the falling edge of the gpio pin asynchronously begins the wakeup procedure, care should be taken to maintain a low-noise environment before entering and during halt mode. e. the wake-up signal fed to a gpio pin to wake up the device must meet the minimum pulse width requirement. furthermore, this signal must be free of glitches. if a noisy signal is fed to a gpio pin, the wake-up behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses. f. once the oscillator has stabilized, the pll lock sequence is initiated, which takes 1 ms. g. when clkin to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. the halt mode is now exited. h. normal operation resumes. i. from the time the idle instruction is executed to place the device into low-power mode (lpm), wakeup should not be initiated until at least four oscclk cycles have elapsed. figure 6-62. halt wake-up using gpion t d(idle?xcol) x1/x2 or xclkin xclkout halt halt wake-up latency flushing pipeline t d(wake?halt device status pll lock-up time normal execution t w(wake-gpio) gpion (i) oscillator start-up time (a) (g) (c) (d)(e) (f) (b) (h) ) t p
155 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 detailed description copyright ? 2010 ? 2016, texas instruments incorporated 6.9.16 universal serial bus (usb) 6.9.16.1 usb electrical data/timing table 6-83. usb input ports dp and dm timing requirements v cc min max unit v(cm) differential input common mode range 0.8 2.5 v z(in) input impedance 300 k vcrs crossover voltage 1.3 2.0 v v il static se input logic-low level 0.8 v v ih static se input logic-high level 2.0 v vdi differential input voltage 0.2 v table 6-84. usb output ports dp and dm switching characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions v cc min max unit v oh d+, d ? single-ended usb 2.0 load conditions 2.8 3.6 v v ol d+, d ? single-ended usb 2.0 load conditions 0 0.3 v z(drv) d+, d ? impedance 28 44 t r rise time full speed, differential, c l = 50 pf, 10%/90%, rpu on d+ 4 20 ns t f fall time full speed, differential, c l = 50 pf, 10%/90%, rpu on d+ 4 20 ns
156 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 applications, implementation, and layout copyright ? 2010 ? 2016, texas instruments incorporated 7 applications, implementation, and layout note information in the following sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. view the important notice for ti designs covering authorized use, intellectual property matters and disclaimers. 7.1 ti design or reference design ti designs reference design library is a robust reference design library spanning analog, embedded processor and connectivity. created by ti experts to help you jump start your system design, all ti designs include schematic or block diagrams, boms and design files to speed your time to market. search and download designs at ti.com/tidesigns . 7.1.1 digitally controlled non-isolated dc/dc buck converter reference design tidm-dc-dc-buck ? this design implements a non-isolated dc/dc buck converter that is digitally controlled using a c2000 microcontroller. the main purpose of this design is to evaluate the powersuite digital power software tools. the design consists of two separate boards: 1) digital power boosterpack ? plug-in module and 2) c2000 f28069m launchpad ? development kit or c2000 f28377s launchpad development kit. 7.1.2 672w highly integrated reference design for automotive bidirectional 48v-12v converter tida-00558 ? today's automotive power consumption is 3kw, which will increase to 10kw in the next 5 years. a 12-v battery is unable to provide that much power. the 48-12v bidirectional convertor provides a high-power requirement solution with two phases, each capable of running 28 a. this solution allows bidirectional current control of both phases using a c2000 control stick and firmware ocp and ovp. the 48-12v bidirectional converter removes the voltage conditioner need and distributes loads more evenly. the 48-v battery is used to power high-torque motors and other high-power components, such as a/c compressors and eps, with no change to 12-v battery loads. 7.1.3 system-on-module for power line communication reference design tidm-somplc-f28plc84 ? the somplc-f28plc84 is a single-board system-on-module (som) for plc in the cenelec frequency band. this single hardware design supports several popular plc industry standards, including prime, g3-plc, and ieee-1901.2. the somplc-f28plc84 replaces the earlier somplc-f28plc83 and is fully hardware- and software-compatible with the earlier design. 7.1.4 g3 power line communications data concentrator on beaglebone black platform tidep0023 ? this power line communications (plc) data concentrator design offers a simplified approach for evaluating g3-plc utilizing beagle bone black powered by the am335x sitara ? processor. users can establish a g3-plc network with one service node. single-phase coupling is supported. 7.1.5 texas instruments ' power line communication developer ' s kit - v3 tidm-tmdsplckit-v3 ? the ti plc developer ? s kit is the best way to evaluate ti ? s plc technology for use in industrial applications such as smart grid ami networks and solar inverters. due to ti ? s flexible plc architecture, this one kit can be used for evaluating several different plc standards (prime, g3, plc lite), allowing developers to choose the plc technology that best fits their application. this developer's kit enables users to perform plc tests on live power networks quickly while making it easier to write their own application software.
157 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 applications, implementation, and layout copyright ? 2010 ? 2016, texas instruments incorporated 7.1.6 dc power line communication (plc) reference design tida-00067 ? the dc (24 v, nominal) power-line communication (plc) reference design is intended as an evaluation module that customers can use to develop end-products for industrial applications, leveraging the capability to deliver both power and communications overs the same dc power line. the reference design provides a complete design guide for the hardware and firmware design of a master (plc) node, slave (plc) node in an extremely small (approximately 1-inch diameter) industrial form factor. 7.2 development tools 7.2.1 f28069 piccolo controlcard tmdscncd28069 ? the c2000 controlcards from texas instruments are ideal products for oems to use for initial software development and short-run builds for system prototypes, test stands, and many other projects that require easy access to high-performance controllers. the controlcards are complete board-level modules that utilize an industry-standard dimm form factor to provide a low-profile, single- board controller solution. all of the c2000 controlcards use the same 100-pin connector footprint to provide the analog and digital i/os on-board controller and are completely interchangeable. the host system needs to provide only a single 5-v power rail to the controlcard for it to be fully functional. 7.2.2 f28069 piccolo controlstick tmds28069usb ? the innovative piccolo controlstick allows quick and easy evaluation all of the advanced capabilities of ti's piccolo microcontroller. slightly larger than a memory stick, the piccolo controlstick features on-board jtag emulation and access to all control peripherals. example projects walk the user through the advanced functionality of piccolo, from simply blinking an led to configuring the high resolution epwm peripherals. 7.2.3 f28069 piccolo experimenter kit tmdsdock28069 ? the c2000 experimenter kits from texas instruments are ideal products for oems to use for initial device exploration and testing. the piccolo f28069 experimenter kit has a docking station that features on-board usb jtag emulation, access to all controlcard signals, breadboard areas and rs-232 and jtag connectors. each kit contains a f28069 controlcard. the controlcard is a complete board-level module that utilizes an industry-standard dimm form factor to provide a low-profile, single- board controller solution. the kit is complete with code composer studio ide and usb cable. 7.3 software tools 7.3.1 controlsuite software suite controlsuite ? controlsuite ? for c2000 microcontrollers is a cohesive set of software infrastructure and software tools designed to minimize software development time. 7.3.2 code composer studio (ccs) integrated development environment (ide) ccstudio ? code composer studio is an integrated development environment (ide) that supports ti's microcontroller and embedded processors portfolio. code composer studio comprises a suite of tools used to develop and debug embedded applications. it includes an optimizing c/c++ compiler, source code editor, project build environment, debugger, profiler, and many other features. 7.3.3 pin mux tool pinmuxtool ? the pin mux utility is a software tool which provides a graphical user interface for configuring pin multiplexing settings, resolving conflicts and specifying i/o cell characteristics for ti mpus.
158 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 applications, implementation, and layout copyright ? 2010 ? 2016, texas instruments incorporated 7.4 training 7.4.1 instaspin-foc launchpad and boosterpack this six-part series provides information about the c2000 instaspin-foc motor control launchpad development kit and boosterpack plug-in module. the instaspin-foc enabled c2000 piccolo launchpad is an inexpensive evaluation platform designed to help you leap right into the world of sensorless motor control using the instaspin-foc solution. part 1: introduction and overview part 2: identifying your motor part 3: zero speed, low speed, & tuning 7.4.2 c2000 architecture and peripherals c2000 architecture and peripherals ? the c2000 family of microcontrollers contains a unique mix of innovative and cutting-edge peripherals along with a very capable c28x core. this video goes over the core architecture and every peripheral offered on c2000 devices. 7.4.3 piccolo control law accelerator (cla) technical overview piccolo control law accelerator (cla) technical overview ? this technical overview of the c2000 piccolo tms320f2803x control law accelerator (cla) that describes how the independent, 32-bit floating-point math accelerator runs in parallel with the c28x core.
159 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 device and documentation support copyright ? 2010 ? 2016, texas instruments incorporated 8 device and documentation support 8.1 device support 8.1.1 development support texas instruments (ti) offers an extensive line of development tools for the c28x generation of mcus, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the following products support development of 2806x-based applications: software development tools ? code composer studio ? integrated development environment (ide) ? c/c++ compiler ? code generation tools ? assembler/linker ? cycle accurate simulator ? application algorithms ? sample applications code hardware development tools ? development and evaluation boards ? jtag-based emulators - xds510 ? class, xds560 ? emulator, xds100 ? flash programming tools ? power supply ? documentation and cables 8.1.1.1 getting started key links include: 1. getting started with c2000 real-time control mcus 2. motor drive & control 3. digital power 4. tools & software for performance mcus 8.1.2 device and development support tool nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all tms320 ? mcu devices and support tools. each tms320 mcu commercial family member has one of three prefixes: tmx, tmp, or tms (for example, tms 320f28069). texas instruments recommends two of three possible prefix designators for its support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (with tmx for devices and tmdx for tools) through fully qualified production devices/tools (with tms for devices and tmds for tools). device development evolutionary flow: tmx experimental device that is not necessarily representative of the final device's electrical specifications tmp final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification tms fully qualified production device
160 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 device and documentation support copyright ? 2010 ? 2016, texas instruments incorporated support tool development evolutionary flow: tmdx development-support product that has not yet completed texas instruments internal qualification testing tmds fully qualified development-support product tmx and tmp devices and tmdx development-support tools are shipped against the following disclaimer: "developmental product is intended for internal evaluation purposes." tms devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti's standard warranty applies. predictions show that prototype devices (tmx or tmp) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also includes a suffix with the device family name. this suffix indicates the package type (for example, pzp) and temperature range (for example, s). figure 8-1 provides a legend for reading the complete device name for any family member. a. for more information on peripheral, temperature, and package availability for a specific device, see table 3-1 . figure 8-1. device nomenclature prefix tms tmx = experimental device tmp = prototype device tms = qualified device 320 device family 320 = tms320 mcu family f technology f = flash 28069 device 2806928068 28067 28066 28065 28064 28063 28062 28069u28068u 28067u 28066u 28065u 28064u 28063u 28062u 28069f28068f 28062f 28069m28068m pzp package type 80-pin pn low-profile quad flatpack (lqfp)10 80-pin pfp powerpad thermally enhanced thin quad flatpack (htqfp) 0-pin pz low-profile quad flatpack (lqfp) 100-pin pzp powerpad thermally enhanced thin quad flatpack (htqfp) temperature range s ?40c to 105c?40c to 125c ?40c to 125c (q refers to q100 qualification for automotive applications.) ts q == =
161 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 device and documentation support copyright ? 2010 ? 2016, texas instruments incorporated 8.2 documentation support extensive documentation supports all of the tms320 mcu family generations of devices from product announcement through applications development. the types of documentation available include: data sheets and data manuals, with design specifications; and hardware and software applications. see the tms320x28xx, 28xxx dsp peripheral reference guide ( spru566 ) for more information on types of peripherals. see the tms320x2806x piccolo technical reference manual ( spruh18 ) for more information about each peripheral. the following documents can be downloaded from the ti website ( www.ti.com ): data manual and errata sprs698 tms320f2806x piccolo ? microcontrollers data manual contains the pinout, signal descriptions, as well as electrical and timing specifications for the 2806x devices. sprz342 tms320f28069, tms320f28068, tms320f28067, tms320f28066, tms320f28065, tms320f28064, tms320f28063, tms320f28062 piccolo mcus silicon errata describes known advisories on silicon and provides workarounds. instaspin technical reference manuals spruhj1 instaspin-foc ? and instaspin-motion ? user's guide describes the instaspin-foc and instaspin-motion devices. spruhi9 tms320f28069f, tms320f28068f, tms320f28062f instaspin-foc ? software technical reference manual describes the tms320f28069f, tms320f28068f, and tms320f28062f instaspin-foc ? software. spruhj0 tms320f28069m, tms320f28068m instaspin-motion ? software technical reference manual describes the tms320f28069m and tms320f28068m instaspin-motion ? software. cpu user's guides spru430 tms320c28x cpu and instruction set reference guide describes the central processing unit (cpu) and the assembly language instructions of the tms320c28x fixed-point digital signal processors (dsps). this reference guide also describes emulation features available on these dsps. peripheral guides and technical reference manuals spru566 tms320x28xx, 28xxx dsp peripheral reference guide describes the peripheral reference guides of the 28x digital signal processors (dsps). spruh18 tms320x2806x piccolo technical reference manual details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the device. tools guides spru513 tms320c28x assembly language tools v15.12.0.lts user's guide describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the tms320c28x device. spru514 tms320c28x optimizing c/c++ compiler v15.12.0.lts user's guide describes the tms320c28x c/c++ compiler. this compiler accepts ansi standard c/c++ source code and produces tms320 dsp assembly language source code for the tms320c28x device. spru608 tms320c28x instruction set simulator technical overview describes the simulator, available within the code composer studio for tms320c2000 ide, that simulates the instruction set of the c28x core. application reports szza021 semiconductor packing methodology describes the packing methodologies employed to prepare semiconductor devices for shipment to end users. sprabx4 calculating useful lifetimes of embedded processors provides a methodology for calculating the useful lifetime of ti embedded processors (eps) under power when used in electronic systems. it is aimed at general engineers who wish to determine if the reliability of the ti ep meets the end system reliability requirement.
162 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 sprs698f ? november 2010 ? revised march 2016 www.ti.com submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 device and documentation support copyright ? 2010 ? 2016, texas instruments incorporated 8.2.1 receiving notification of document updates to receive notification of documentation updates ? including silicon errata ? go to the product folder for your device on ti.com . in the upper right-hand corner, click the "alert me" button. this registers you to receive a weekly digest of product information that has changed (if any). for change details, check the revision history of any revised document. 8.3 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 8-1. related links parts product folder sample & buy technical documents tools & software support & community tms320f28069 click here click here click here click here click here tms320f28068 click here click here click here click here click here tms320f28067 click here click here click here click here click here tms320f28066 click here click here click here click here click here tms320f28065 click here click here click here click here click here tms320f28064 click here click here click here click here click here tms320f28063 click here click here click here click here click here tms320f28062 click here click here click here click here click here 8.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. ti embedded processors wiki texas instruments embedded processors wiki. established to help developers get started with embedded processors from texas instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 8.5 trademarks powerpad, piccolo, tms320c2000, c2000, controlsuite, boosterpack, launchpad, sitara, code composer studio, xds510, xds560, tms320, instaspin-foc, instaspin-motion, e2e are trademarks of texas instruments. i 2 c-bus is a registered trademark of nxp b.v. corporation. all other trademarks are the property of their respective owners. 8.6 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.7 glossary ti glossary this glossary lists and explains terms, acronyms, and definitions.
163 tms320f28069 , tms320f28068 , tms320f28067 , tms320f28066 tms320f28065 , tms320f28064 , tms320f28063 , tms320f28062 www.ti.com sprs698f ? november 2010 ? revised march 2016 submit documentation feedback product folder links: tms320f28069 tms320f28068 tms320f28067 tms320f28066 tms320f28065 tms320f28064 tms320f28063 tms320f28062 mechanical packaging and orderable information copyright ? 2010 ? 2016, texas instruments incorporated 9 mechanical packaging and orderable information 9.1 packaging information the following pages include mechanical packaging and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
mechanical data mtqf010a january 1995 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pn (s-pqfp-g80) plastic quad flatpack 4040135 / b 11/96 0,17 0,27 0,13 nom 40 21 0,25 0,45 0,75 0,05 min seating plane gage plane 41 60 61 80 20 sq sq 1 13,80 14,20 12,20 9,50 typ 11,80 1,45 1,35 1,60 max 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
mechanical data mtqf013a october 1994 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pz (s-pqfp-g100) plastic quad flatpack 4040149 /b 11/96 50 26 0,13 nom gage plane 0,25 0,45 0,75 0,05 min 0,27 51 25 75 1 12,00 typ 0,17 76 100 sq sq 15,80 16,20 13,80 1,35 1,45 1,60 max 14,20 0 7 seating plane 0,08 0,50 m 0,08 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026

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package option addendum www.ti.com 1-feb-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tms320f28062fpfpq active htqfp pfp 80 96 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28062fpfpq tms320 tms320f28062fpnt active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28062fpnt tms320 tms320f28062fpzt active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28062fpzt tms320 tms320f28062pfpq active htqfp pfp 80 96 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28062pfpq tms320 TMS320F28062PFPQR active htqfp pfp 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28062pfpq tms320 tms320f28062pfps active htqfp pfp 80 96 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28062pfps tms320 tms320f28062pnt active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 320f28062pnt tms tms320f28062pzpq active htqfp pzp 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28062pzpq tms320 tms320f28062pzps active htqfp pzp 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28062pzps tms320 tms320f28062pzt active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 320f28062pzt tms tms320f28062upnt active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 320f28062upnt tms tms320f28062upzt active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28062upzt tms320 tms320f28063pfpq preview htqfp pfp 80 96 tbd call ti call ti -40 to 125 tms320f28063pnt active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 320f28063pnt tms tms320f28063pzt active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 320f28063pzt tms tms320f28064pfpq preview htqfp pfp 80 96 tbd call ti call ti -40 to 125 tms320f28064pzpq preview htqfp pzp 100 90 tbd call ti call ti -40 to 125 tms320f28064pzt active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 320f28064pzt tms tms320f28065pfpq preview htqfp pfp 80 96 tbd call ti call ti -40 to 125
package option addendum www.ti.com 1-feb-2018 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tms320f28065pfps active htqfp pfp 80 96 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28065pfps tms320 tms320f28065pnt active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28065pnt tms320 tms320f28065pzpq active htqfp pzp 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28065pzpq tms320 tms320f28065pzps active htqfp pzp 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28065pzps tms320 tms320f28065pzt active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 320f28065pzt tms tms320f28065upfps active htqfp pfp 80 96 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28065upfps tms320 tms320f28065upnt active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28065upnt tms320 tms320f28065upzps active htqfp pzp 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28065upzps tms320 tms320f28065upzt active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28065upzt tms320 tms320f28066pfpq active htqfp pfp 80 96 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28066pfpq tms320 tms320f28066pfps active htqfp pfp 80 96 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28066pfps tms320 tms320f28066pnt active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 320f28066pnt tms tms320f28066pzpq active htqfp pzp 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28066pzpq tms320 tms320f28066pzps active htqfp pzp 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28066pzps tms320 tms320f28066pzt active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 320f28066pzt tms tms320f28066upzt active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28066upzt tms320 tms320f28067pfpq active htqfp pfp 80 96 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28067pfpq tms320 tms320f28067pfps active htqfp pfp 80 96 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28067pfps tms320
package option addendum www.ti.com 1-feb-2018 addendum-page 3 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tms320f28067pnt active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 320f28067pnt tms tms320f28067pzpq active htqfp pzp 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28067pzpq tms320 tms320f28067pzps active htqfp pzp 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28067pzps tms320 tms320f28067pzt active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 320f28067pzt tms tms320f28068fpfpq active htqfp pfp 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28068fpfpq tms320 tms320f28068fpnt active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28068fpnt tms320 tms320f28068fpzt active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28068fpzt tms320 tms320f28068mpfpq active htqfp pfp 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28068mpfpq tms320 tms320f28068mpnt active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28068mpnt tms320 tms320f28068mpzt active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28068mpzt tms320 tms320f28068pfpq preview htqfp pfp 80 96 tbd call ti call ti -40 to 125 tms320f28068pnt active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 320f28068pnt tms tms320f28068pzpq preview htqfp pzp 100 90 tbd call ti call ti -40 to 125 tms320f28068pzps active htqfp pzp 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28068pzps tms320 tms320f28069fpfpq active htqfp pfp 80 96 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28069fpfpq tms320 tms320f28069fpnt active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28069fpnt tms320 tms320f28069fpzpq active htqfp pzp 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28069fpzpq tms320 tms320f28069fpzt active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28069fpzt tms320 tms320f28069mpfpq active htqfp pfp 80 96 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28069mpfpq tms320
package option addendum www.ti.com 1-feb-2018 addendum-page 4 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tms320f28069mpnt active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28069mpnt tms320 tms320f28069mpzpq active htqfp pzp 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28069mpzpq tms320 tms320f28069mpzt active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28069mpzt tms320 tms320f28069pfpq active htqfp pfp 80 96 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28069pfpq tms320 tms320f28069pfps active htqfp pfp 80 96 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28069pfps tms320 tms320f28069pnt active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 320f28069pnt tms tms320f28069pza active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 320f28069pza tms tms320f28069pzpq active htqfp pzp 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28069pzpq tms320 tms320f28069pzps active htqfp pzp 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28069pzps tms320 tms320f28069pzt active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 320f28069pzt tms tms320f28069upfps active htqfp pfp 80 96 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28069upfps tms320 tms320f28069upnt active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28069upnt tms320 tms320f28069upzps active htqfp pzp 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 f28069upzps tms320 tms320f28069upzt active lqfp pz 100 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 f28069upzt tms320 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device.
package option addendum www.ti.com 1-feb-2018 addendum-page 5 (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TMS320F28062PFPQR htqfp pfp 80 1000 330.0 24.4 15.0 15.0 1.5 20.0 24.0 q2 package materials information www.ti.com 2-feb-2018 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TMS320F28062PFPQR htqfp pfp 80 1000 367.0 367.0 55.0 package materials information www.ti.com 2-feb-2018 pack materials-page 2
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